4.3.41. Data Fault Status Register

The DFSR characteristics are:

Purpose

Holds status information about the last data fault.

Usage constraints

The DFSR is:

  • A read/write register.

  • Banked for Secure and Non-secure states.

  • Accessible from PL1 or higher.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 4.6.

There are two formats for this register. The current translation table format determines which format of the register is used. This section describes:

DFSR when using the Short-descriptor translation table format

Figure 4.34 shows the DFSR bit assignments when using the Short-descriptor translation table format.

Figure 4.34. DFSR bit assignments for Short-descriptor translation table format

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Table 4.67 shows the DFSR bit assignments when using the Short-descriptor translation table format.

Table 4.67. DFSR bit assignments for Short-descriptor translation table format

BitsNameFunction
[31:14]-

Reserved, UNK/SBZP.

[13]CM

Cache maintenance fault. For synchronous faults, this bit indicates whether a cache maintenance operation generated the fault:

0

Abort not caused by a cache maintenance operation.

1

Abort caused by a cache maintenance operation.

[12]ExT

External abort type. This field indicates whether an AXI Decode or Slave error caused an abort:

0

External abort marked as DECERR.

1

External abort marked as SLVERR.

For aborts other than external aborts this bit always returns 0.

[11]WnR

Write not Read bit. This field indicates whether the abort was caused by a write or a read access:

0

Abort caused by a read access.

1

Abort caused by a write access.

For faults on CP15 cache maintenance operations, including the VA to PA translation operations, this bit always returns a value of 1.

[10]FS[4]Part of the Fault Status field. See bits [3:0] in this table.
[9]-

RAZ.

[8]-

Reserved, UNK/SBZP.

[7:4]Domain

Specifies which of the 16 domains, D15-D0, was being accessed when a data fault occurred.

For permission faults that generate Data Abort exception, this field is Unknown. ARMv7 deprecates any use of the domain field in the DFSR.

[3:0]FS[3:0]

Fault Status bits. This field indicates the type of exception generated, any encoding not listed is reserved:

0b00001

Alignment fault.

0b00010

Debug event.

0b00011

Access flag fault, section.

0b00100

Instruction cache maintenance fault.

0b00101

Translation fault, section.

0b00110

Access flag fault, page.

0b00111

Translation fault, page.

0b01000

Synchronous external abort, non-translation.

0b01001

Domain fault, section.

0b01011

Domain fault, page.

0b01100

Synchronous external abort on translation table walk, 1st level.

0b01101

Permission fault, section.

0b01110

Synchronous external abort on translation table walk, 2nd level.

0b01111

Permission fault, page.

0b10110

Asynchronous external abort.


DFSR when using the Long-descriptor translation table format

Figure 4.35 shows the DFSR bit assignments when using the Long-descriptor translation table format.

Figure 4.35. DFSR bit assignments for Long-descriptor translation table format

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Table 4.68 shows the DFSR bit assignments when using the Long-descriptor translation table format.

Table 4.68. DFSR bit assignments for Long-descriptor translation table format

BitsNameFunction
[31:14]-

Reserved, UNK/SBZP.

[13]CM

Cache maintenance fault. For synchronous faults, this bit indicates whether a cache maintenance operation generated the fault:

0

Abort not caused by a cache maintenance operation.

1

Abort caused by a cache maintenance operation.

[12]ExT

External abort type. This field indicates whether an AXI Decode or Slave error caused an abort:

0

External abort marked as DECERR.

1

External abort marked as SLVERR.

For aborts other than external aborts this bit always returns 0.

[11]WnR

Write not Read bit. This field indicates whether the abort was caused by a write or a read access:

0

Abort caused by a read access.

1

Abort caused by a write access.

For faults on CP15 cache maintenance operations, including the VA to PA translation operations, this bit always returns a value of 1.

[10]-Reserved, UNK/SBZP.
[9]-

RAO.

[8:6]-

Reserved, UNK/SBZP.

[5:0]Status

Fault Status bits. This field indicates the type of exception generated. Any encoding not listed is reserved.

0b0001LL

Translation fault, LL bits indicate level.

0b0010LL

Access fault flag, LL bits indicate level.

0b0011LL

Permission fault, LL bits indicate level.

0b010000

Synchronous external abort.

0b010001

Asynchronous external abort.

0b0101LL

Synchronous external abort on translation table walk, LL bits indicate level.

0b100001

Alignment fault.

0b100010

Debug event.


Table 4.69 shows how the LL bits in the Status field encode the lookup level associated with the MMU fault.

Table 4.69. Encodings of LL bits associated with the MMU fault

BitsMeaning
0b00Reserved
0b01Level 1
0b10Level 2
0b11Level 3

To access the DFSR, read or write the CP15 register with:

MRC p15, 0, <Rt>, c5, c0, 0; Read Data Fault Status Register
MCR p15, 0, <Rt>, c5, c0, 0; Write Data Fault Status Register
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