4.3.7. Processor Feature Register 0

The ID_PFR0 characteristics are:

Purpose

Provides information about the programmers model and top-level information about the instruction sets supported by the processor.

Usage constraints

The ID_PFR0 is:

  • A read-only register.

  • Common to the Secure and Non-secure states.

  • Only accessible from PL1 or higher.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 4.2.

Figure 4.6 shows the ID_PFR0 bit assignments.

Figure 4.6. ID_PFR0 bit assignments

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Table 4.34 shows the ID_PFR0 bit assignments.

Table 4.34. ID_PFR0 bit assignments

BitsNameFunction
[31:16]-

Reserved, RAZ.

[15:12]State3

Indicates support for Thumb Execution Environment (ThumbEE) instruction set:

0x1

ThumbEE instruction set implemented.

[11:8]State2

Indicates support for Jazelle extension:

0x1

Processor supports trivial implementation of Jazelle extension.

[7:4]State1

Indicates support for Thumb instruction set:

0x3

Processor supports Thumb encoding after the introduction of Thumb-2 technology, and for all 16-bit and 32-bit Thumb basic instructions.

[3:0]State0

Indicates support for ARM instruction set:

0x1

Processor supports ARM instruction set.


To access the ID_PFR0, read the CP15 register with:

MRC p15, 0, <Rt>, c0, c1, 0; Read Processor Feature Register 0
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