A.9.2. MBIST interface

Table A.23 shows the MBIST interface signals.

Table A.23. MBIST interface signals

Signal nameDirectionDescription
MBISTACKOutputMBIST test acknowledge
MBISTADDR[13:0]InputMBIST logical address in array
MBISTARRAY[8:0]InputMBIST array selector
MBISTBE[3:0]InputMBIST bit write enable
MBISTCFGInputMBIST all RAMs enable
MBISTINDATA[85:0]InputMBIST data in
MBISTOUTDATA[85:0]OutputMBIST data out
MBISTREADENInputMBIST Read enable
MBISTREQInputMBIST test request
MBISTWRITEENInputMBIST write enable
nMBISTRESETInputMBIST reset

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