4.3.31. Auxiliary Control Register

The ACTLR characteristics are:

Purpose

Provides implementation defined configuration and control options for the processor.

Usage constraints

The ACTLR is:

  • A read/write register.

  • Common to the Secure and Non-secure states.

  • Only accessible from PL1 or higher, with access rights that depend on the mode:

    • Read/write in Secure PL1 modes.

    • Read-only and write-ignored in Non-secure PL1 and PL2 modes if NSACR.NS_SMP is 0.

    • Read/write in Non-secure PL1 and PL2 modes if NSACR.NS_SMP is 1. In this case, all bits are write-ignored except for the SMP bit.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 4.3.

Figure 4.27 shows the ACTLR bit assignments.

Figure 4.27. ACTLR bit assignments

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Table 4.60 shows the ACTLR bit assignments.

Table 4.60. ACTLR bit assignments

BitsNameFunction
[31:29]-

Reserved, RAZ/WI.

[28]DDI

Disable dual issue:

0

Enables dual issue, this is the reset value.

1

Disables dual issue.

[27:16]-

Reserved, RAZ/WI.

[15]DDVM

Disable Distributed Virtual Memory (DVM) transactions:

0

Enables DVM, this is the reset value.

1

Disables DVM.

[14:13]L1PCTL

L1 Data prefetch control. The value of this field determines the maximum number of outstanding data prefetches permitted in the L1 memory system, not counting those generated by software load or PLD instructions:

0b00

Prefetch disabled.

0b01

1 outstanding pre-fetch permitted.

0b10

2 outstanding pre-fetches permitted.

0b11

3 outstanding pre-fetches permitted, this is the reset value.

[12]L1RADIS

L1 Data Cache read-allocate mode disable[a]:

0

Enables L1 data cache read-allocate mode, this is the reset value.

1

Disables L1 data cache read-allocate mode.

[11]L2RADIS

L2 Data Cache read-allocate mode disable[a]:

0

Enables L2 data cache read-allocate mode, this is the reset value.

1

Disables L2 data cache read-allocate mode.

[10]DODMBS

Disable optimized data memory barrier behavior:

0

Enables optimized data memory barrier behavior, this is the reset value.

1

Disables optimized data memory barrier.

[9:7]-

Reserved, RAZ/WI.

[6]SMP

Enables coherent requests to the processor:

0

Disables coherent requests to the processor. This is the reset value.

1

Enables coherent requests to the processor.

When coherent requests are disabled:

  • loads to cacheable memory are not cached by the processor.

  • Load-Exclusive instructions take a precise abort if the memory attributes are:

    • Inner Write-Back and Outer Shareable.

    • Inner Write-Through and Outer Shareable.

    • Outer Write-Back and Outer Shareable.

    • Outer Write-Through and Outer Shareable.

    • Inner Write-Back and Inner Shareable.

    • Inner Write-Through and Inner Shareable.

    • Outer Write-Back and Inner Shareable.

    • Outer Write-Back and Inner Shareable.

Note

You must ensure this bit is set to 1 before the caches and MMU are enabled, or any cache and TLB maintenance operations are performed. The only time this bit is set to 0 is during a processor power-down sequence. See Power management.

[5:0]-

Reserved, RAZ/WI.

[a] See Data Cache Unit for more information.


To access the ACTLR, read or write the CP15 register with:

MRC p15, 0, <Rt>, c1, c0, 1 ; Read Auxiliary Control Register
MCR p15, 0, <Rt>, c1, c0, 1 ; Write Auxiliary Control Register
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