4.2. Register summary

This section gives a summary of the CP15 system control registers. See the ARM Architecture Reference Manual for more information on using the CP15 system control registers.

The system control coprocessor is a set of registers that you can write to and read from. Some of the registers permit more than one type of operation.

The following sections describe the CP15 system control registers grouped by CRn order, and are accessed by the MCR and MRC instructions in the order of CRn, Op1, CRm, Op2:

The Cortex-A7 MPCore processor supports the Virtualization Extensions (VE) and the Large Physical Address Extension (LPAE). See Virtualization Extensions architecture and Large Physical Address Extension architecture and Chapter 9 Generic Timer for more information. The VE, LPAE, and Generic Timer contain a number of 64-bit registers. The following subsection describes these registers and provides cross references to individual register descriptions:

This section also summarizes the CP15 system control registers by functional groups:

Table 4.1 describes the column headings in the CP15 register summary tables use throughout this section.

Table 4.1. System control register field values

HeadingDescription
CRnPrimary register number within the system control coprocessor
Op1Opcode_1 value for the register
CRmOperational register number within CRn
Op2Opcode_2 value for the register
Nameform architectural, operation, or code name for the register
ResetReset value of register
DescriptionCross-reference to register description

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