4.3.22. Cache Level ID Register

The CLIDR characteristics are:

Purpose

Identifies:

  • The type of cache, or caches, implemented at each level.

  • The Level of Coherency and Level of Unification for the cache hierarchy.

Usage constraints

The CLIDR is:

  • A read-only register.

  • Common to the Secure and Non-secure states.

  • Only accessible from PL1 or higher.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 4.2.

Figure 4.19 shows the CLIDR bit assignments.

Figure 4.19. CLIDR bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 4.48 shows the CLIDR bit assignments.

Table 4.48. CLIDR bit assignments

BitsNameFunction
[31:30]-

Reserved, RAZ.

[29:27]LoUU

Indicates the Level of Unification Uniprocessor for the cache hierarchy:

0x1

L2 cache.

[26:24]LoC

Indicates the Level of Coherency for the cache hierarchy:

0b001

L2 cache not implemented on the processor.

0b010

L2 cache coherency.

[23:21]LoUIS

Indicates the Level of Unification Inner Shareable for the cache hierarchy:

0b001

L2 cache.

[20:6]-Reserved, RAZ.
[5:3]Ctype2

Indicates the type of cache if the processor implements level 2 cache:

0b000

L2 cache not implemented on the processor.

0b100

Unified instruction and data caches.

[2:0]Ctype1

Indicates the type of cache implemented at level 1:

0b011

Separate instruction and data caches.


To access the CLIDR, read the CP15 register with:

MRC p15, 1, <Rt>, c0, c0, 1 ; Read Cache Level ID Register
Copyright © 2011, 2012 ARM. All rights reserved.ARM DDI 0464E
Non-ConfidentialID112412