4.3.19. Instruction Set Attribute Register 4

The ID_ISAR4 characteristics are:

Purpose

Provides information about the instruction set that the processor supports beyond the basic set.

Usage constraints

The ID_ISAR4 is:

  • A read-only register.

  • Common to the Secure and Non-secure states.

  • Only accessible from PL1 or higher.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 4.2.

Figure 4.17 shows the ID_ISAR4 bit assignments.

Figure 4.17. ID_ISAR4 bit assignments

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Table 4.45 shows the ID_ISAR4 bit assignments.

Table 4.45. ID_ISAR4 bit assignments

BitsNameFunction
[31:28]SWP_frac

Indicates support for the memory system locking the bus for SWP or SWPB instructions:

0x1

Processor supports SWP and SWPB instruction but only in a uniprocessor context. SWP and SWPB do not guarantee whether memory accesses from other masters can come between the load memory access and the store memory access of the SWP or SWPB instruction.

[27:24]PSR_M_instrs

Indicates the supported M profile instructions to modify the PSRs:

0x0

None supported.

[23:20]SynchPrim_instrs_frac

This field is used with the SynchPrim_instrs field of ID_ISAR3 to indicate the supported Synchronization Primitive instructions:

0x0

Processor supports:

  • LDREX and STREX instructions.

  • CLREX, LDREXB, LDREXH, STREXB, and STREXH instructions.

  • LDREXD and STREXD instructions.

[19:16]Barrier_instrs

Indicates the supported Barrier instructions in the ARM and Thumb instruction sets:

0x1

Processor supports DMB, DSB, and ISB barrier instructions.

[15:12]SMC_instrs

Indicates the supported SMC instructions:

0x1

Processor supports SMC instruction.

[11:8]Writeback_instrs

Indicates support for Write-Back addressing modes:

0x1

Processor supports all Write-Back addressing modes defined in ARMv7 architecture.

[7:4]WithShifts_instrs

Indicates support for instructions with shifts.

0x4

Processor supports:

  • Shifts of loads and stores over the range LSL 0-3.

  • Constant shift options, both on load/store and other instructions.

  • Register-controlled shift options.

[3:0]Unpriv_instrs

Indicates the supported unprivileged instructions.

0x2

Processor supports:

  • LDRBT, LDRT, STRBT, and STRT instructions.

  • LDRHT, LDRSBT, LDRSHT, and STRHT instructions.


To access the ID_ISAR4, read the CP15 register with:

MRC p15, 0, <Rt>, c0, c2, 4 ; Read Instruction Set Attribute Register 4
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