A.8.3. Miscellaneous Debug signals

Table A.19 shows the miscellaneous Debug signals. All signals which include a 4-bit field, [3:0], encode up to four processors. For these signals, bit[0] represents processor 0, bit[1] represents processor 1, bit[2] represents processor 2, and bit[3] represents processor 3.

Table A.19. Miscellaneous Debug signals

SignalDirectionDescription
COMMRX[3:0]Output

Communications channel receive. Receive portion of Data Transfer Register full flag:

0

Empty.

1

Full.

COMMTX[3:0]Output

Communication transmit channel. Transmit portion of Data Transfer Register empty flag:

0

Full.

1

Empty.

APBACTIVE[3:0]Output

Processor debug busy.

0

Not active.

1

Active.

DBGACK[3:0]Output

Debug acknowledge:

0

External debug request not acknowledged.

1

External debug request acknowledged.

DBGOSUNLOCKCATCH[3:0] Input

Debug OS unlock catch enable:

0

Debug OS unlock catch disabled.

1

Debug OS unlock catch enabled.

DBGHALTREQ[3:0]Input

Debug halt request:

0

No debug halt request.

1

Debug halt request.

DBGLOCKSET[3:0]Input

Debug software lock status:

0

Lock clear.

1

Lock set.

DBGHOLDRST[3:0]Input

Debug hold core warm reset:

0

Processor is not held in reset after a power-up or warm reset.

1

Processor is held in reset after a power-up or warm reset.

DBGSWENABLE[3:0]Input

Debug software access enable:

0

Not enabled.

1

Enabled, access by the software through the Extended CP14 interface is permitted.

EDBGRQ[3:0]Input

External debug request:

0

No external debug request.

1

External debug request.

The processor treats the EDBGRQ input as level-sensitive. The EDBGRQ input must be asserted until the processor asserts DBGACK.

DBGROMADDR[39:12]Input

Specifies bits [39:12] of the ROM table physical address.

If the address cannot be determined, tie this signal off to 0.

This pin is only sampled during reset of the processor.

DBGROMADDRVInput

Valid signal for DBGROMADDR.

If the address cannot be determined, tie this signal LOW.

This pin is only sampled during reset of the processor.

DBGSELFADDR[39:15]Input

Specifies bits [39:15] of the two’s complement signed offset from the ROM table physical address to the physical address where the debug registers are memory-mapped.

If the offset cannot be determined, tie this signal off to 0.

This pin is only sampled during reset of the processor.

DBGSELFADDRVInput

Valid signal for DBGSELFADDR. If the offset cannot be determined, tie this signal LOW.

This pin is only sampled during reset of the processor.

DBGRESTART[3:0]InputExternal restart requests
DBGRESTARTED[3:0]OutputHandshake for DBGRESTART.
DBGTRIGGER[3:0]OutputDebug external request taken.

Copyright © 2011, 2012 ARM. All rights reserved.ARM DDI 0464E
Non-ConfidentialID112412