7.2. Snoop Control Unit

Cortex-A7 MPCore processor supports between one and four individual processors with L1 data cache coherency maintained by the SCU. The SCU is clocked synchronously and at the same frequency as the processors.

The SCU maintains coherency between the individual data caches in the processor using ACE modified equivalents of MOESI state, as described in Data Cache Unit.

The SCU contains buffers that can handle direct cache-to-cache transfers between processors without having to read or write any data to the external memory system. Cache line migration enables dirty cache lines to be transferred directly between processors while remaining in the MOESI modified state, and there is no requirement to write back transferred cache line data to the external memory system.

Each processor has tag and dirty RAMs that contain the MOESI state of the cache line. Rather than access these for each snoop request the SCU contains a set of duplicate tags that permit each coherent data request to be checked against the contents of the other caches in the cluster. The duplicate tags filter coherent requests from the system so that the processors and system can function efficiently even with a high volume of snoops from the system.

When an external snoop hits in the duplicate tags a request is made to the appropriate processor. The processor prioritizes external requests from the SCU over internal requests from the DPU.

The SCU also controls snoop and maintenance requests to the system using the external BROADCASTINNER, BROADCASTOUTER, and BROADCASTCACHEMAINT pins:

Note

  • If you set the BROADCASTINNER pin to 1 you must also set the BROADCASTOUTER pin to 1.

  • In a system that contains Cortex-A15 and Cortex-A7 MPCore processor clusters, you must ensure the BROADCASTINNER and BROADCASTOUTER pins on both processor clusters are set to 1 so that both clusters are in the same Inner Shareable domain.

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