7.4. Optional integrated L2 cache

The optional integrated L2 configurable caches sizes are 128KB, 256KB, 512KB, and 1MB.

Data is only allocated to the L2 cache when evicted from the L1 memory system, not when first fetched from the system. The L1 cache can prefetch data from the system without data being evicted from the L2 cache.

Instructions are allocated to the L2 cache when fetched from the system and can be invalidated from the L2 during maintenance operations.

The L2 cache is 8-way set associative. The L2 cache tags are looked up in parallel with the SCU duplicate tags. If both the L2 tag and SCU duplicate tag hit the L2 tag hit takes priority.

Additionally, speculative requests to the system from the SCU are not made until the system checks the L2 cache.

L2 RAMs are invalidated automatically at reset unless the L2RSTDISABLE signal is set HIGH when the nL2RESET signal is deasserted.

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