10.4.3. Debug Run Control Register

The DBGDRCR characteristics are:

Purpose

Software uses this register to:

  • Request the processor to enter or exit Debug state

  • Clear to 0 the sticky exception bits in the DBGDSCR, see the ARM Architecture Reference Manual for information on the DBGDSCR.

Usage constraints

The DBGDRCR is accessible when the processor is powered off. DBGDRCR is not accessible on extended CP14 interface.

Configurations

Required in all implementations.

Attributes

See the register summary in Table 10.1.

Figure 10.4 shows the DBGDRCR bit assignments.

Figure 10.4. DBGDRCR bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 10.4 shows the DBGDRCR bit assignments.

Table 10.4. DBGDRCR bit assignments

BitsNameFunction
[31:5]-

Reserved, SBZ.

[4]CBRRQ

Cancel Bus Requests Request. The actions on writing to this bit are:

0

No action.

1

Request cancel of pending accesses.

[3]CSPA

Clear Sticky Pipeline Advance bit. This bit sets the DBGDSCR.PipeAdv bit to 0. The actions on writing to this bit are:

0

No action.

1

Sets the DBGDSCR.PipeAdv bit to 0.

When the processor is powered down, it is unpredictable whether a write of 1 to this bit sets DBGDSCR.PipeAdv to 0.

[2]CSE

Clear Sticky Exceptions bits. This bit sets the DBGDSCR sticky exceptions bits to 0. The actions on writing to this bit are:

0

No action.

1

Sets the DBGDSCR[8:6] to 0b000.

See the ARM Architecture Reference Manual for more information on the DBGDSCR.

[1]RRQ

Restart request. The actions on writing to this bit are:

0

No action.

1

Request exit from Debug state.

Writing 1 to this bit requests that the processor exits Debug state. This request is held until the processor exits Debug state. After the request has been made, the debugger can poll the DBGDSCR.RESTARTED bit until it reads as 1.

The processor ignores writes to this bit if it is in Non-debug state.

[0]HRQ

Halt request. The actions on writing to this bit are:

0

No action.

1

Request exit from Debug state.

Writing 1 to this bit requests that the processor enters Debug state. This request is held until the processor enters Debug state.

After the request has been made, the debugger can poll the DBGDSCR.HALTED bit until it reads 1.

The processor ignores writes to this bit if it is already in Debug state.


Copyright © 2011, 2012 ARM. All rights reserved.ARM DDI 0464E
Non-ConfidentialID112412