10.4.22. Debug Peripheral Identification Registers

The Debug Peripheral Identification Registers provide standard information required for all components that conform to the ARM Debug Interface v5 specification. They are a set of eight registers, listed in register number order in Table 10.24.

Table 10.24. Summary of the Debug Peripheral Identification Registers

RegisterValueOffset
Debug Peripheral ID40x040xFD0
Debug Peripheral ID50x000xFD4
Debug Peripheral ID60x000xFD8
Debug Peripheral ID70x000xFDC
Debug Peripheral ID00x070xFE0
Debug Peripheral ID10xBC0xFE4
Debug Peripheral ID2[a]0x4B0xFE8
Debug Peripheral ID30x000xFEC

[a] Bits [7:4] of this value match the revision field in the Debug Identification Register, see Debug Identification Register.


Only bits [7:0] of each Debug Peripheral ID Register are used, with bits [31:8] reserved. Together, the eight Debug Peripheral ID Registers define a single 64-bit Debug Peripheral ID.

The ARM Architecture Reference Manual describes these registers.

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