10.3. Debug register summary

Table 10.1 shows the 32-bit or 64-bit wide CP14 interface registers, accessed by the MCR, MRC, MCCR, or MRRC instructions in the order of CRn, Op1, CRm, Op2.

Table 10.1. CP14 debug register summary

Register numberOffsetCRnOp1CRmOp2NameTypeDescription
00x000c00c00DBGDIDRRODebug Identification Register
10x004c00c10DBGDSCR internal viewRODebug Status and Control Register, see the ARM Architecture Reference Manual
2-40x008-0x010------Reserved
50x014c00c50DBGDTRTX internal viewWOTarget to Host Data Transfer Register, see the ARM Architecture Reference Manual
      DBGDTRRX internal viewROHost to Target Data Transfer Register, see the ARM Architecture Reference Manual
60x018c00c60DBGWFAR-UNK/SBZP
70x01Cc00c70DBGVCRRWVector Catch Register, see the ARM Architecture Reference Manual
80x020------Reserved
90x024----DBGECRRWEvent Catch Register, see the ARM Architecture Reference Manual
100x028c00c100--Not implemented
110x02Cc00c110--Not implemented
12-310x030-0x07C------Reserved
320x080c00c02DBGDTRRX external viewRWHost to Target Data Transfer Register, see the ARM Architecture Reference Manual
330x084----DBGITRWOInstruction Transfer Register, see the ARM Architecture Reference Manual
DBGPCSRROProgram Counter Sampling Register
340x088c00c22DBGDSCR external viewRWDebug Status and Control Register, see the ARM Architecture Reference Manual
350x08Cc00c32DBGDTRTX external viewRWTarget to Host Data Transfer Register, see the ARM Architecture Reference Manual
360x090----DBGDRCRWODebug Run Control Register
370x094----DBGEACRRWDebug External Auxiliary Control Register
38-390x098-0x09C------Reserved
400x0A0----DBGPCSRROProgram Counter Sampling Register
410x0A4----DBGCIDSRROContext ID Sampling Register, see the ARM Architecture Reference Manual
420x0A8----DBGVIDSRROVirtualization ID Sampling Register, see the ARM Architecture Reference Manual
43-630x0AC-0x0FC------Reserved
64-690x100-0x114c00c0-c54DBGBVRnRWBreakpoint Value Registers
70-710x118-0x11C------Reserved
72-790x120-0x13C------Reserved
80-850x140-0x154c00c0-c55DBGBCRnRWBreakpoint Control Registers
86-950x158-0x17C------Reserved
96-990x180-0x18Cc00c0-c36DBGWVRnRWWatchpoint Value Registers
100-1110x190-0x1BC------Reserved
112-1150x1C0-0x1CCc00c0-c37DBGWCRnRWWatchpoint Control Registers
116-1270x1D0-0x1FC ------Reserved
1280x200------Reserved
129-1470x204-0x24C------Reserved
148-1490x250-0x254c10c4-c51DBGBXVRnRWBreakpoint Extended Value Registers
150-1910x258-0x2FC------Reserved
1920x300c10c04DBGOSLARWOOS Lock Access Register
1930x304c10c14DBGOSLSRROOS Lock Status Register
1940x308------Not implemented
1950x30C------Reserved
1960x310c10c44DBGPRCRRWDevice Power-down and Reset Control Register
1970x314----DBGPRSRRODevice Powerdown and Reset Status Register, see the ARM Architecture Reference Manual
198-2550x318-0x03C------Reserved
256-5110x400-0x7FC------Reserved
512-5750x800-0x8FC------Reserved
576-8310x900-0xCFC------Reserved
832-8950xD00-0xDFC----Processor ID registersROProcessor ID registers, see the ARM Architecture Reference Manual
896-9270xE00-0xE7C------Reserved
928-9570xE80-0xEF4------Reserved
9580xEF8----DBGITMISCOUTWOIntegration Miscellaneous Signals Register
9590xEFC----DBGITMISCINROIntegration Miscellaneous Signals Input Register
9600xF00----DBGITCTRLRWIntegration Mode Control Register
961-9990xF04-0xF9C------Reserved
10000xFA0c70c86DBGCLAIMSETRWClaim Tag Set Register
10010xFA4c70c96DBGCLAIMCLRRWClaim Tag Clear Register
1002-10030xFA8-0xFAC------Reserved
10040xFB0----DBGLARWOLock Access Register, see the ARM Architecture Reference Manual
10050xFB4----DBGLSRROLock Status Register, see the ARM Architecture Reference Manual
10060xFB8c70c146DBGAUTHSTATUSROAuthentication Status Register, see the ARM Architecture Reference Manual
10070xFBC------Reserved
10080xFC0c70c07DBGDEVID2ROUNK
10090xFC4c70c17DBGDEVID1RODebug Device ID Register 1
10100xFC8c70c27DBGDEVIDRODebug Device ID Register
10110xFCC----DBGDEVTYPERODevice Type Register, see the ARM Architecture Reference Manual
10120xFD0----DBGPID4RODebug Peripheral Identification Registers
1013-10150xFD4-0xFDC----DBGPID5-7-Reserved
10160xFE0----DBGPID0RODebug Peripheral Identification Registers
10170xFE4----DBGPID1RO
10180xFE8----DBGPID2RO
10190xFEC----DBGPID3RO
10200xFF0----DBGCID0RODebug Component Identification Registers
10210xFF4----DBGCID1RO
10220xFF8----DBGCID2RO
10230xFFC----DBGCID3RO
--c00c10DBGDSCR internal viewRO

Debug Status and Control Register, see the ARM Architecture Reference Manual

--c00c50DBGDTRRX internal viewWO

Host to Target Data Transfer, see the ARM Architecture Reference Manual

      DBGDTRTX internal viewRO

Target to Host Transfer, see the ARM Architecture Reference Manual

--c10c00DBGDRAR (MRC)RODebug ROM Address Register
c10 DBGDRAR (MRRC)RODebug ROM Address Register
--c10c34DBGOSDLRRW

OS Double Lock Register, see the ARM Architecture Reference Manual

--c20c00DBGDSAR (MRC)RODebug Self Address Offset Register
c20 DBGDSAR (MRRC)RODebug Self Address Offset Register

Copyright © 2011, 2012 ARM. All rights reserved.ARM DDI 0464E
Non-ConfidentialID112412