8.2.1. GIC memory-map

The GIC registers are memory-mapped, and the base address is specified by PERIPHBASE[39:15]. This input must be tied to a constant value. The PERIPHBASE value is sampled during reset into the Configuration Base Address (CBAR) for each processor in the cluster. See Configuration Base Address Register.

Memory regions used for these registers must be marked as Device or Strongly-ordered in the translation tables.

Memory regions marked as Normal Memory cannot access any of the GIC registers, instead access caches or external memory as required.

Table 8.1 lists the address offsets for the GIC blocks relative to the PERIPHBASE base address. Access to reserved regions can result in a data abort exception to the requesting processor.

Table 8.1. GIC memory map

Offset from PERIPHBASE[39:15]GIC block
0x2000-0x3FFFCPU interface
0x4000-0x4FFFVirtual interface control, common base address
0x5000-0x5FFFVirtual interface control, processor-specific base address
0x6000-0x7FFFVirtual CPU interface

The GIC provides two aliases of the GIC virtual interface control registers:

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