11.4.2. Performance Monitors Peripheral Identification Registers

The Performance Monitors Peripheral Identification Registers provide standard information required for all components that conform to the ARM PMUv2 architecture. They are a set of eight registers, listed in register number order in Table 11.3.

Table 11.3. Summary of the Performance Monitors Peripheral Identification Registers

RegisterValueOffset
Performance Monitors Peripheral ID40x040xFD0
Performance Monitors Peripheral ID50x000xFD4
Performance Monitors Peripheral ID60x000xFD8
Performance Monitors Peripheral ID70x000xFDC
Performance Monitors Peripheral ID00xA70xFE0
Performance Monitors Peripheral ID10xB90xFE4
Performance Monitors Peripheral ID20x4B0xFE8
Performance Monitors Peripheral ID30x000xFEC

Only bits [7:0] of each Performance Monitors Peripheral ID Register are used, with bits [31:8] reserved. Together, the eight Performance Monitors Peripheral ID Registers define a single 64-bit Peripheral ID.

The ARM Architecture Reference Manual describes these registers.

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