11.4.1. Performance Monitor Control Register

The PMCR characteristics are:

Purpose
  • Provides details of the performance monitor implementation, including the number of counters implemented.

  • Configures and controls the counters.

Usage constraints

The PMCR is:

  • A read/write register.

  • Common to the Secure and Non-secure states.

  • Accessible from PL1 or higher.

  • accessible in User mode only when the PMUSERENR.EN bit is set to 1.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 11.1.

Figure 11.2 shows the PMCR bit assignments.

Figure 11.2. Performance Monitor Control Register bit assignments

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Table 11.2 shows the PMCR bit assignments.

Table 11.2. PMCR bit assignments

BitsNameFunction
[31:24]IMP

Implementer code.

0x41

ARM.

This is a read-only field.

[23:16]IDCODE

Identification code.

0x07

Cortex-A7 MPCore identification code.

This is a read-only field.

[15:11]N

Number of event counters. In Secure state and Hyp mode, this field returns 0x4 that indicates the number of counters implemented.

In Non-secure modes other than Hyp mode, this field reads the value of HDCR.HPMN. See Hyp Debug Control Register.

This is a read-only field.

[10:6]-

Reserved, UNK/SBZP.

[5]DP

Disable cycle counter, PMCCNTR, in regions of software when prohibited:

0

Count is enabled in prohibited regions. This is the reset value.

1

Count is disabled in prohibited regions. This bit is read/write.

[4]X

Export enable. This bit permits events to be exported to another debug device, such as a trace macrocell, over an event bus:

0

Export of events is disabled. This is the reset value.

1

Export of events is enabled. This bit is read/write.

[3]D

Clock divider:

0

When enabled, PMCCNTR counts every clock cycle. This is the reset value.

1

When enabled, PMCCNTR counts once every 64 clock cycles.

This bit is read/write.

[2]C

Clock counter reset:

0

No action. This is the reset value.

1

Reset PMCCNTR to 0.

This bit is write-only, and always RAZ.

[1]P

Event counter reset:

0

No action. This is the reset value.

1

Reset all event counters, not including PMCCNTR, to 0.

In Non-secure modes other than Hyp mode, writing a 1 to this bit does not reset event counters that the HDCR.HPMN field reserves for Hyp mode use. See Hyp Debug Control Register.

In Secure state and Hyp mode, writing a 1 to this bit resets all event counters.

This bit is write-only, and always RAZ.

[0]E

Enable bit. Performance monitor overflow IRQs are only signaled when the enable bit is set to 1.

0

All counters, including PMCCNTR, are disabled. This is the reset value.

1

All counters are enabled.

This bit is read/write.


To access the PMCR, read or write the CP15 registers with:

MRC p15, 0, <Rt>, c9, c12, 0; Read Performance Monitor Control Register
MCR p15, 0, <Rt>, c9, c12, 0; Write Performance Monitor Control Register
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