2.4.2. Power modes

The power domains can be controlled independently to give different combinations of power-up and power-down domains. However, only some power-up and power-down domain combinations are valid and supported.

Table 2.2 .shows the supported power configurations for the different possible modes of operation.

Table 2.2. Supported power modes

ModeVsocVscuVscu_ramVcore<n[a]>
Run modePowered upPowered upPowered upPowered up
Processor n[a] in shutdown modePowered upPowered upPowered upPowered down
Cortex-A7 MPCore processor in shutdown modePowered upPowered downPowered downPowered down
Cortex-A7 MPCore processor in Dormant modePowered upPowered downPowered upPowered down

[a] Where n represents 0-3.


There are specific requirements that you must meet to power up and power down each power domain within the processor. Not adhering to these requirements can lead to unpredictable results.

The dynamic power management and power-up and power-down sequences in the following sections are the only power sequences that ARM recommends. Any deviation from these sequences can lead to unpredictable results.

The supported power modes are:

Run mode

This is the normal mode of operation where all of the processor functionality is available. The Cortex-A7 MPCore processor uses gated clocks and gates to disable inputs to unused functional blocks. Only the logic in use to perform an operation consumes any dynamic power.

Standby mode

The following sections describes the methods of entering standby mode:

Processor Wait for Interrupt

Wait for Interrupt is a feature of the ARMv7-A architecture that puts the processor in a low power state by disabling most of the clocks in the processor while keeping the processor powered up. This reduces the power drawn to the static leakage current, leaving a small clock power overhead to enable the processor to wake up from WFI mode.

A processor enters into WFI mode by executing the WFI instruction.

When executing the WFI instruction, the processor waits for all instructions in the processor to retire before entering the idle or low power state. The WFI instruction ensures that all explicit memory accesses occurred before the WFI instruction in program order, have retired. For example, the WFI instruction ensures that the following instructions received the required data or responses from the L2 memory system:

  • Load instructions.

  • Cache and TLB maintenance operations.

  • Store exclusives instructions.

In addition, the WFI instruction ensures that store instructions have updated the cache or have been issued to the L2 memory system.

While the processor is in WFI mode, the clocks in the processor are temporarily enabled without causing the processor to exit WFI mode, when any of the following events are detected:

  • An L2 snoop request that must be serviced by the processor L1 data cache.

  • A cache or TLB maintenance operation that must be serviced by the processor L1 instruction cache, data cache, or TLB.

  • An APB access to the debug or trace registers residing in the processor power domain.

Exit from WFI mode occurs when the processor detects a reset or one of the WFI wake up events as described in the ARM Architecture Reference Manual.

On entry into WFI mode, STANDBYWFI for that processor is asserted. Assertion of STANDBYWFI guarantees that the processor is in idle and low power state. STANDBYWFI continues to assert even if the clocks in the processor are temporarily enabled because of an L2 snoop request, cache, or TLB maintenance operation or an APB access.

Figure 2.4 shows the upper bound for the STANDBYWFI deassertion timing after the assertion of nIRQ or nFIQ inputs.

Figure 2.4. STANDBYWFI deassertion timing

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Processor Wait for Event

Wait for Event is a feature of the ARMv7-A architecture that uses a locking mechanism based on events to put the processor in a low power state by disabling most of the clocks in the processor while keeping the processor powered up. This reduces the power drawn to the static leakage current, leaving a small clock power overhead to enable the processor to wake up from WFE mode.

A processor enters into WFE mode by executing the WFE instruction. When executing the WFE instruction, the processor waits for all instructions in the processor to complete before entering the idle or low power state.

While the processor is in WFE mode, the clocks in the processor are temporarily enabled without causing the processor to exit WFE mode, when any of the following events are detected:

  • An L2 snoop request that must be serviced by the processor L1 data cache.

  • A cache or TLB maintenance operation that must be serviced by the processor L1 instruction cache, data cache, or TLB.

  • An APB access to the debug or trace registers residing in the processor power domain.

Exit from WFE mode occurs when the processor detects a reset, the assertion of the EVENTI input signal, or one of the WFI wake up events as described in the ARM Architecture Reference Manual.

On entry into WFE mode, STANDBYWFE for that processor is asserted. Assertion of STANDBYWFE guarantees that the processor is in idle and low power state. STANDBYWFE continues to assert even if the clocks in the processor are temporarily enabled because of an L2 snoop request, cache, and TLB maintenance operation or an APB access.

The upper bound for the STANDBYWFE deassertion timing after the assertion of nIRQ or nFIQ inputs is identical to STANDBYWFI as shown in Figure 2.4.

L2 Wait for Interrupt

When all the processors are in WFI mode, the shared L2 memory system logic that is common to all the processors can also enter a WFI mode. In L2 WFI mode, all internal clocks in the processor are disabled.

Entry into L2 WFI mode can only occur if specific requirements are met and the following sequence applied:

  • All processors are in WFI mode and therefore, all the processors STANDBYWFI outputs are asserted. Assertion of all the processors STANDBYWFI outputs guarantee that all the processors are in idle and low power state. All clocks in the processor, with the exception of a small amount of clock wake up logic, are disabled.

  • The SoC asserts the input pin ACINACTM to idle the AXI master interface. This prevents the L2 memory system from accepting any new requests from the AXI master interface.

  • When the L2 memory system completed the outstanding transactions for AXI interfaces, it can then enter the low power state, L2 WFI mode. On entry into L2 WFI mode, STANDBYWFIL2 is asserted. Assertion of STANDBYWFIL2 guarantees that the L2 memory system is in idle and does not accept any new transactions.

Exit from L2 WFI mode occurs on one of the following WFI wake up events:

  • A physical IRQ or FIQ interrupt.

  • A debug event.

  • Power-on or soft reset.

When the processor exits from WFI mode, STANDBYWFI for that processor is deasserted. When the L2 memory system logic exits from WFI mode, STANDBYWFIL2 is deasserted. The SoC must continue to assert ACINACTM until STANDBWFIL2 has deasserted.

Figure 2.5 shows the L2 WFI timing for a 4-processor configuration.

Figure 2.5. L2 Wait For Interrupt timing

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Individual processor shutdown mode

This is the mode where the Vcore power domain for an individual processor is shut down and all state is lost.

To enable a processor to be powered down, the implementation must place the processor on a separately controlled power supply. In addition, you must clamp the outputs of the processor to benign values while the entire processor is powered down, to indicate that the processor is idle.

To power down the processor, apply the following sequence:

  1. Clear the SCTLR.C bit, or HSCTLR.C bit if in Hyp mode, to prevent further data cache allocation.

  2. Clean and invalidate all data from the L1 data cache. The L2 duplicate snoop tag RAM for this processor is now empty. This prevents any new data cache snoops or data cache maintenance operations from other processors in the multiprocessor device being issued to this processor.

  3. Execute a CLREX instruction.

  4. Switch the processor from Symmetric Multiprocessing (SMP) mode to Asymmetric Multiprocessing (AMP) mode by clearing the ACTLR.SMP bit. Clearing the SMP bit enables the processor to be taken out of coherency by preventing the processor from receiving cache or TLB maintenance operations broadcast by other processors in the multiprocessor device.

  5. Execute an ISB instruction to ensure that all of the CP15 register changes from the previous steps have been committed.

  6. Execute a DSB instruction to ensure that all cache, TLB and branch predictor maintenance operations issued by any processor in the multiprocessor device before the SMP bit was cleared have completed.

  7. Execute a WFI instruction and wait until the STANDBYWFI output is asserted to indicate that the processor is in idle and low power state.Deassert DBGPWRDUP LOW. This prevents any external debug access to the processor.

    Note

    The DBGPWRDUP signal is an integration layer signal. See the Cortex-A7 MPCore Integration Manual for more information.

  8. Activate the processor output clamps.

  9. Remove power from the Vcore power domain.

To power up the processor, apply the following sequence:

  1. Assert nCOREPORESET LOW and hold L1RSTDISABLE LOW. Ensure DBGPWRDUP is held LOW to prevent any external debug access to the processor.

  2. Apply power to the Vcore power domain. Keep the state of the signals nCOREPORESET, L1RSTDISABLE and DBGPWRDUP LOW.

  3. When the power domain has stabilized and reset has been asserted for four or more cycles, release the processor output clamps.

  4. De-assert resets.

  5. Assert DBGPWRDUP HIGH to allow external debug access to the processor.

  6. If required use software to restore the state of the processor prior to power-down.

  7. Assert ACTLR.SMP bit HIGH for SMP mode. Continue a normal power-on reset sequence.

Note

The DBGPWRDUP signal is an integration layer signal. See the Cortex-A7 MPCore Integration Manual for more information.

Multiprocessor device shutdown mode

This is the mode where the Vscu, Vscu_ram, and Vcore power domains are shut down and all state is lost. To power down the multiprocessor device, apply the following sequence:

  1. Ensure all non-lead processors are in shutdown mode, see Individual processor shutdown mode.

  2. Follow steps 1. to 3. in Individual processor shutdown mode.

  3. Clean and invalidate all data from L2 data cache.

  4. Follow steps 4 to 9. in Individual processor shutdown mode.

  5. Assert ACINACTM and wait until the STANDBYWFIL2 output is asserted to indicate that the L2 memory system is idle.

  6. Activate the multiprocessor device output clamps.

  7. Remove power from the Vscu and Vscu_ram power domains.

Note

For device power-down, all operations on a lead processor must occur after the equivalent step on all non-lead processors.

To power up the multiprocessor device, apply the following sequence:

  1. For each processor in the multiprocessor device, assert nCOREPORESET LOW and hold L1RSTDISABLE LOW.

  2. For the lead processor in the multiprocessor device, assert nL2RESET LOW and hold L2RSTDISABLE LOW.

  3. Apply power to the Vscu, Vscu_ram, and Vcore domains while keeping the signals described in steps 1. and 2. LOW.

  4. When the power domain has stabilized and reset has been asserted for four or more cycles, release the processor output clamps.

  5. Continue a normal power-on reset sequence.

  6. For each processor in the multiprocessor device, set the ACTLR.SMP bit to 1 for SMP mode.

    Note

    You must ensure the ACTLR.SMP bit is set to 1 before the caches and MMU are enabled, or any cache and TLB maintenance operations are performed. The only time this bit is set to 0 is during a processor power-down sequence.

Dormant mode

Optionally, the Dormant mode is supported in the multiprocessor device. In this mode all the processors and L2 control logic are powered down while the L2 cache RAMs are powered up and retain state. The RAM blocks that remain powered up during Dormant mode are:

  • L2 tag RAMs.

  • L2 data RAMs.

To support Dormant mode, you must ensure:

  • That the L2 cache RAMs are in a separate power domain.

  • To clamp all inputs to the L2 cache RAMs to benign values. This avoids corrupting data when the processors and L2 control power domains enter and exit power down state.

Before entering Dormant mode the architectural state of the multiprocessor device, excluding the contents of the L2 cache RAMs that remain powered up, must be saved to external memory.

To exit from Dormant mode to Run mode, the SoC must perform a full power-on reset sequence. The SoC must assert the reset signals until power is restored. After power is restored, the processor exits the power-on reset sequence, and the architectural state must be restored.

To enter Dormant mode, apply the following sequence:

  1. Clear the SCTLR C bit to prevent further data cache allocation.

  2. Clean and invalidate all data from the L1 data cache. The L2 duplicate snoop tag RAM for this processor is now empty. This prevents any new data cache snoops or data cache maintenance operations from other processors in the multiprocessor device being issued to this processor.

  3. Execute a CLREX instruction.

  4. Switch the processor from SMP mode to AMP mode by clearing the ACTLR.SMP bit. Clearing the SMP bit enables the processor to be taken out of coherency by preventing the processor from receiving cache or TLB maintenance operations broadcast by other processors in the multiprocessor device.

  5. Save architectural state, if required. These state saving operations must ensure that the following occur:

    • All ARM registers, including the CPSR and SPSR, are saved.

    • All system registers are saved.

    • All debug related state is saved.

  6. Execute an ISB instruction to ensure that all of the CP15 register changes from the previous steps have been committed.

  7. Execute a DSB instruction to ensure that all cache, TLB and branch predictor maintenance operations issued by any processor in the multiprocessor device before the SMP bit was cleared have completed. In addition, this ensures that all state saving has completed.

  8. Execute a WFI instruction and wait until the STANDBYWFI output is asserted, to indicate that the processor is in idle and low power state.

  9. Repeat the previous steps for all processors, and wait for all STANDBYWFI outputs to be asserted.

  10. Assert ACINACTM and wait until the STANDBYWFIL2 output is asserted to indicate that the L2 memory system is idle.

  11. When all processors STANDBYWFI and STANDBYWFIL2 are asserted, the multiprocessor device is ready to enter Dormant mode.

  12. Activate the L2 cache RAM input clamps.

  13. Remove power from the Vcore and Vscu power domains.

To exit Dormant mode, apply the following sequence:

  1. Apply a normal power-on reset sequence. You must apply resets to the processors and the L2 memory system logic until power is restored. During this reset sequence, L2RSTDISABLE must be held HIGH to disable the L2 cache hardware reset mechanism.

  2. When power has been restored and reset has been asserted for four or more clock cycles, release the L2 cache RAM input clamps.

  3. Continue a normal power-on reset sequence with L2RSTDISABLE held HIGH.

  4. The architectural state must be restored, if required.

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