6.6. Direct access to internal memory

The Cortex-A7 MPCore processor provides a mechanism to read the internal memory used by the Cache and TLB structures through the implementation-defined region of the system coprocessor interface. This functionality can be useful when investigating issues where the coherency between the data in the cache and data in system memory is broken.

The appropriate memory block and location is selected using a number of write-only CP15 registers and the data is read from read-only CP15 registers as shown in Table 6.2. These operations are only available in secure privileged modes. In all other modes, executing the CP15 instruction results in an Undefined Instruction exception.

Table 6.2. Cortex-A7 MPCore system coprocessor CP15 registers used to access internal memory

FunctionAccessCP15 operationRd Data
Data Register 0Read-onlyMRC p15, 3, <Rd>, c15, c0, 0Data
Data Register 1Read-onlyMRC p15, 3, <Rd>, c15, c0, 1Data
Data Register 2Read-onlyMRC p15, 3, <Rd>, c15, c0, 2Data
Data Cache Tag Read Operation RegisterWrite-onlyMCR p15, 3, <Rd>, c15, c2, 0Set/Way
Instruction Cache Tag Read Operation RegisterWrite-onlyMCR p15, 3, <Rd>, c15, c2, 1Set/Way
Data Cache Data Read Operation RegisterWrite-onlyMCR p15, 3, <Rd>, c15, c4, 0Set/Way/Offset
Instruction Cache Data Read Operation RegisterWrite-onlyMCR p15, 3, <Rd>, c15, c4, 1Set/Way/Offset
TLB Data Read Operation RegisterWrite-onlyMCR p15, 3, <Rd>, c15, c4, 2Index/Way

The following sections describe the encodings for the operations and the format for the data read from the memory:

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