6.4.1. Internal exclusive monitor

The Cortex-A7 MPCore L1 memory system has an internal exclusive monitor. This is a two-state, open and exclusive, state machine that manages load/store exclusive (LDREXB, LDREXH, LDREX, LDREXD, STREXB, STREXH, STREX, and STREXD) accesses and clear exclusive (CLREX) instructions. You can use these instructions to construct semaphores, ensuring synchronization between different processes running on the processor, and also between different processors that are using the same coherent memory locations for the semaphore. A Load-Exclusive instruction tags a small block of memory for exclusive access. The size of the tagged block is defined by CTR.ERG as 16 words, one cache line.

A Load-Exclusive instruction that causes a transaction with ARLOCK[0] set to 1 is expected to receive an EXOKAY response. An OKAY response to a transaction with ARLOCK[0] set to 1 indicates that exclusive accesses are not supported at the address of the transaction and causes a precise abort to be taken. A Load-Exclusive instruction causes ARLOCK[0] to be set to 1 if the memory attributes are:

A Load-Exclusive instruction might also take a precise abort if ACTLR.SMP bit is clear. See Table 4.60 for more information.

See the ARM Architecture Reference Manual for more information about these instructions.

Treatment of intervening STR operations

In cases where there is an intervening STR operation in an LDREX/STREX code sequence, the intermediate STR does not produce any direct effect on the internal exclusive monitor. The local monitor is in the Exclusive Access state after the LDREX, remains in the Exclusive Access state after the STR, and returns to the Open Access state only after the STREX.

However, if the address LDREX/STREX code sequence is in cacheable memory, any eviction of the cache line containing that address clears the monitor. It is therefore recommended that no load or store instructions are placed between the LDREX and STREX because these additional instructions can cause a cache eviction. Any data cache maintenance instruction can also clear the exclusive monitor.

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