2.3.1. Clocking

The Cortex-A7 MPCore processor has a single clock input, CLKIN. All processors in the Cortex-A7 MPCore processor and the SCU are clocked with a distributed version of CLKIN. The Cortex-A7 MPCore processor synchronizes the input signals:

All other external signals must be synchronous with reference to CLKIN.

ACE master interface clocking

The SCU interface supports integer ratios of the CLKIN frequency , for example 1:1, 2:1, 3:1. These ratios are configured through external clock enable signals. In all cases AXI transfers remain synchronous. The ACE master interface includes the ACLKENM clock enable signal.

ACLKENM asserts one CLKIN cycle prior to the rising edge of the external ACE clock signal, ACLKM. Software can change the CLKIN to ACLKM frequency ratio dynamically using ACLKENM.

Figure 2.2 shows a timing example of ACLKENM that changes the CLKIN to ACLKM frequency ratio from 3:1 to 1:1.

Figure 2.2. ACLKENM with CLKIN:ACLKM ratio changing from 3:1 to 1:1

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Note

Figure 2.2 shows the timing relationship between the AXI master clock, ACLKM and ACLKENM, where ACLKENM asserts one clock cycle before the rising edge of ACLKM. It is important that the relationship between ACLKM and ACLKENM is maintained.

Debug interface clocking

The processor includes an APB interface to access the debug and performance monitoring registers. Internally this interface is driven from CLKIN. A separate enable signal, PCLKENDBG, is provided to enable the external APB bus to be driven at a lower frequency, which must be an integer ratio of CLKIN. If the debug infrastructure in the system is required to be fully asynchronous to the processor clock, you can use a synchronizing component to connect the external AMBA APB to the processor.

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