Appendix B. Revisions

This appendix describes the technical changes between released issues of this book.

Table B.1. Issue A

ChangeLocationAffects

First release

--

Table B.2. Differences between issue A and issue B

ChangeLocationAffects
Clarified reset signal descriptionsResetsAll
Updated valid reset combinationsTable 2.1All

Updated reset value of the Main ID Register

Table 4.2

Table 4.16

r0p1
Updated bits[3:0] of the Main ID RegisterMain ID Registerr0p1
Updated descriptions for Processor Feature Register 0 bits[15:12] and bits[11:8]Processor Feature Register 0All
Clarified the CSSELR value and the complete register encoding for L1 instruction cache and L1 instruction cache selection in the CCSIDRTable 4.47All
Clarified BROADCASTCACHEMAINT pin descriptionSnoop Control UnitAll
Enhancement in the use of nVFIQ and nVIRQ signals

GIC configuration

Table A.3

r0p1
Clarified DBGDIDR, DBGPCSR, DBGBVR, DBGDRAR, and DBGDSAR register descriptionsChapter 10 DebugAll

Updated the value for Peripheral ID2 register

Table 10.24

Table 11.3

r0p1
Renamed PMCCFILTR to PMXEVTYPER31 in the PMU register summary tableTable 11.1All

Updated the EVENTI and EVENTO signal descriptions

Table A.5All
Clarified the DBGHOLDRST[3:0] signal descriptionTable A.19All

Table B.3. Differences between issue B and issue C

ChangeLocationAffects
Added the Debug an Performance Monitors Peripheral ID2 Register valuesProduct revisionsr0p1
Clarified the power-down sequences

Individual processor shutdown mode

Dormant mode

All

Updated the reset value of the Main ID Register

Table 4.2

Table 4.16

r0p2
Updated the PRRR, NMRR, MAIR0 and MAIR1 reset values

Table 4.11

Table 4.17

All
Clarified the ID_ISAR0.Divide_instrs bit descriptionTable 4.41All
Added PRRR description

Primary Region Remap Register

All
Added MAIR0 and MAIR1 descriptionMAIR0 and MAIR1, Memory Attribute Indirection Registers 0 and 1All
Added NMRR descriptionNormal Memory Remap RegisterAll
Updated bits[3:0] of the Main ID RegisterMain ID Registerr0p2
Updated the ACTLR.DDI bit descriptionTable 4.60All
Clarified the CPACR.ASEDIS bit descriptionTable 4.61All
Clarified the SCR.nET bit and SCR.NS bit descriptionsTable 4.62All
Clarified the NSACR.cp11 bit and the NSACR.cp10 bit descriptionsTable 4.63All
Updated the type of exceptions reported in the DFSR

Table 4.67

Table 4.68

All
Updated the type of exceptions reported in the IFSR

Table 4.70

Table 4.71

All
Added memory region attributes descriptionMemory region attributes on page 5-3All
Updated the representation of the BROADCASTINNER, BROADCASTOUTER, BROADCASTCACHEMAINT, and SYSBARDISABLE signalsTable 7.1All
Added the key features in each of the supported ACE configurationsTable 7.2All
Updated write and read issuing capability commentsTable 7.3All
Clarified the DBGOSLSR.OSLK bit descriptionTable 10.14All

Clarified the peripheral and component ID registers used for Debug

Debug Peripheral Identification Registers

Debug Component Identification Registers

All

Clarified the peripheral and component ID registers used for Performance Monitors

Performance Monitors Peripheral Identification Registers

Performance Monitors Component Identification Registers

All
Updated the Debug Peripheral ID2 valueTable 10.24r0p2
Updated the Performance Monitors Peripheral ID2 valueTable 11.3r0p2

Table B.4. Differences between issue C and issue D

ChangeLocationAffects
Changed the number of consecutive cache line sized writes to enter secondary read allocate mode from seven to 127. Also clarified the secondary read allocate mode description.Data side memory systemr0p3
Updated the power up and power down sequences required for individual processor shutdown modeIndividual processor shutdown modeAll

Updated the reset value of the Main ID Register.

Table 4.2

Table 4.16

r0p3
Clarified SCTLR reset value.Table 4.3All
Clarified access to system control registers when CRn is c7.Table 4.8All
Updated the CCSIDR usage constraints.Cache Size ID RegisterAll
Updated the CPACR usage constraints.Coprocessor Access Control RegisterAll

Clarified the use of the SCTLR.Z bit.

Table 4.52 All
Updated bits[3:0] of the Main ID Register.Main ID Registerr0p3
Updated the ACTLR.SMP bit description.Table 4.60All

Updated CPACR.D32DIS bit description. This bit is UNK/SBZP for implementations with VFP and Advanced SIMD, only r0p3 and later versions enforce this.

Table 4.61r0p3

Updated NSACR.NSD32DIS bit description. This bit is UNK/SBZP for implementations with VFP and Advanced SIMD, but only r0p3 enforces this.

Table 4.63r0p3
Clarified ACE transactions.Table 6.1All
Clarified Main TLB descriptor memory type and shareability encodingsTable 6.9All
Clarified how the Load-Exclusive instruction affects the internal exclusive monitor.Internal exclusive monitorAll
Clarified the use of registers that are offset 0xF10-0xFFC in the GIC Distributor.Table 8.3All
Updated the Debug Peripheral ID2 value.Table 10.24r0p3
Updated the Performance Monitors Peripheral ID2 value.Table 11.3r0p3
Updated the nFIQ[3:0] and nIRQ[3:0] signal descriptions.Generic Interrupt Controller signalsAll
Clarified snoop response channel signals.Table A.14All

Table B.5. Differences between issue D and issue E

ChangeLocationAffects

Clarified input signals synchronized by the Cortex-A7 MPCore processor.

ClockingAll
Added recommendation that the reset signals are asserted for at least four CLKIN cycles.ResetsAll
Updated the processor power down sequence.

Individual processor shutdown mode

Multiprocessor device shutdown mode

All
Clarified the sequences required for both entering and exiting Dormant mode.Dormant modeAll

Clarified how the STANDBYWFI[3:0] and STANDBYWFIL2 signals are used to communicate between the Cortex-A7 MPCore processor and the system power management controller.

Communication to the Power Management ControllerAll
Combined the ThumbEE architecture section with the Jazelle Extension section from Chapter 3 Programmers Model into one section called Execution environment support.

Execution environment support

All

Updated reset value of the Main ID Register.

Table 4.2

Table 4.16

r0p4
Added clarification to the description of the PoU and PoC footnotes.

Table 4.8

Table 4.21

All
Updated bits[3:0] of the Main ID Register.Main ID Registerr0p4
Clarified the value the LoC field takes to indicate L2 cache is not implemented on the processor.Table 4.48All
Clarified the Coprocessor Access Control Register description.Coprocessor Access Control RegisterAll
Clarified the Non-Secure Access Control Register description.Non-Secure Access Control RegisterAll
Clarified the HDCR.TDRA, TDOSA, TDA, and TDE bit field descriptions.Table 4.65All
Clarified the HSR.EC and IL bit field descriptions.Table 4.73All
Added a footnote about not using SCTLR bit encodings TEX = 001, C = 1, and B = 0. This is to insure compatibility with other processors.Table 5.1All
Combined the Memory types section with the Attributes section from Chapter 5 Memory Management Unit into one section called Memory types and attributes.Memory types and attributesAll
Clarified the Walk cache RAM description.Walk cache RAMAll
Updated synchronous and asynchronous aborts description.Synchronous and asynchronous abortsAll
Clarified the instruction cache speculative memory accesses description.Instruction cache speculative memory accessesAll
Clarified the SYSBARDISABLE signal setting for non-AXI3 modes, that is AXI configurations.

Table 7.1

AXI3 Compatibility mode

All

Updated the GICD_IIDR value.

Table 8.3r0p4
Updated the GICD_IIDR.ProductID bit field value.Table 8.5All
Updated the GICD_IIDR.Revision bit field value.Table 8.5r0p4
Updated the GICC_IIDR value.Table 8.8r0p4
Updated the GICC_IIDR.Revision bit field value.Table 8.10r0p4
Updated the GICV_IIDR value.Table 8.13r0p4
Clarified the DBGPCSR.PCS and T bit field descriptions.Table 10.3All
Clarified the DBGBVR usage constraints and attributes.Breakpoint Value RegistersAll
Clarified the DBGBCR.BT, LBN, SCC, BAC, PMC, and E bit field descriptions.Table 10.8All
Clarified the DBGWVR purpose, usage constraints, and attributes.Watchpoint Value RegistersAll
Clarified the DBGWCR usage constraints and attributes.Watchpoint Control RegistersAll
Clarified the DBGWCR.MASK, WT, LBN, SCC, HMC, PAC, and E bit field descriptions.Table 10.10All
Updated the DBGOSLAR.OS Lock Access bit description.Table 10.13All
Updated the Debug Peripheral ID2 value.Table 10.24r0p4
Correct register name Debug Device ID Register 0. Debug Device ID Registerr0p4
Updated the Performance Monitors Peripheral ID2 value.Table 11.3r0p4
Removed the asynchronous terminology from the nFIQ, nIRQ, nVFIQ, and nVIRQ descriptions.Table A.3All

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