Using this book

This book is organized into the following chapters:

Chapter 1 Introduction

Read this for an introduction to the Cortex-A7 MPCore processor and descriptions of the major features.

Chapter 2 Functional Description

Read this for a description of the functionality of the Cortex-A7 MPCore processor.

Chapter 3 Programmers Model

Read this for a description of the programmers model.

Chapter 4 System Control

Read this for a description of the system control registers, their structure, operation, and how to use them.

Chapter 5 Memory Management Unit

Read this for a description of the Memory Management Unit (MMU) and the address translation process.

Chapter 6 L1 Memory System

Read this for a description of the Level 1 (L1) memory system, including caches, Translation Lookaside Buffers (TLB), and store buffer.

Chapter 7 L2 Memory System

Read this for a description of the Level 2 (L2) memory system, including the Snoop Control Unit (SCU) and the AXI Coherency Extensions (ACE) attributes.

Chapter 8 Generic Interrupt Controller

Read this for a description of the Generic Interrupt Controller (GIC).

Chapter 9 Generic Timer

Read this for a description of the timers.

Chapter 10 Debug

Read this for a description of the support for debug.

Chapter 11 Performance Monitoring Unit

Read this for a description of the Performance Monitoring Unit (PMU) and associated events.

Appendix A Signal Descriptions

Read this for a description of the input and output signals.

Appendix B Revisions

Read this for a description of the technical changes between released issues of this book.

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