A.7.1. Clock and configuration signals

Table A.6 shows the clock and configuration signals for the ACE master interface.

Table A.6. Clock and configuration signals

SignalDirectionDescription
ACLKENMInputAXI master bus clock enable. See Clocking for more information.
ACINACTMInputSnoop interface is inactive and no longer accepting requests.
BROADCASTINNER[a]Input

Enable broadcasting of Inner Shareable transactions:

0

Inner Shareable transactions are not broadcasted externally.

1

Inner Shareable transactions are broadcasted externally.

If BROADCASTINNER is tied HIGH, you must also tie BROADCASTOUTER HIGH.

BROADCASTOUTER[a]Input

Enable broadcasting of outer shareable transactions:

0

Outer Shareable transactions are not broadcasted externally.

1

Outer Shareable transactions are broadcasted externally.

BROADCASTCACHEMAINT[a]Input

Enable broadcasting of cache maintenance operations to downstream caches:

0

Cache maintenance operations are not broadcasted to downstream caches.

1

Cache maintenance operations are broadcasted to downstream caches.

SYSBARDISABLE[a][b][c]Input

Disable broadcasting of barriers onto system bus:

0

Barriers are broadcast onto system bus, this requires an AMBA4 interconnect.

1

Barriers are not broadcast onto the system bus. This is compatible with an AXI3 interconnect.

[a] This pin is only sampled during reset of the processor. See Table 7.1 for more information.

[b] For AXI3 compatibility, SYSBARDISABLE must be tied HIGH and BROADCASTINNER, BROADCASTOUTER, and BROADCASTCACHEMAINT must be tied LOW.

[c] When SYSBARDISABLE is asserted, the system that the Cortex-A7 processor is connected to must meet the multicopy atomicity requirements. These requirements are:

  • Writes to the same location are observed in the same order by all agents.

  • A write to a location which is observable to one agent, is observable by all agents.


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