4.3.49. L2 Control Register

The L2CTLR characteristics are:

Purpose

Defines the implemented options of the multiprocessor device.

Usage constraints

The L2CTLR is:

  • A read only register.

  • Common to the Secure and Non-secure states.

  • accessible from PL1 or higher.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 4.6.

Figure 4.39 shows the L2CTLR bit assignments.

Figure 4.39. L2CTLR bit assignments

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Table 4.74 shows the L2CTLR bit assignments.

Table 4.74. L2CTLR bit assignments

BitsNameFunction
[31:26]-

Reserved, RAZ/WI.

[25:24]Number of processors

Number of processors present:

0b00

One processor, Processor 0.

0b01

Two processors, Processor 0 and Processor 1.

0b10

Three processors, Processor 0, Processor 1, and Processor 2.

0b11

Four processors, Processor 0, Processor 1, Processor 2, and Processor 3.

These bits are read-only and the reset value of this field is set to the number of processors present in the configuration.

[23]Interrupt controller

Interrupt controller:

0

Interrupt Controller not present.

1

Interrupt Controller present.

[22:1] 

Reserved, RAZ/WI.

0]Data RAM latency

L2 data RAM latency:

0

2 cycles.

1

3 cycles.


To access the L2CTLR, read the CP15 register with:

MRC p15, 1, <Rt>, c9, c0, 2; Read L2 Control Register
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