4.3.21. Cache Size ID Register

The CCSIDR characteristics are:

Purpose

Provides information about the architecture of the caches.

Usage constraints

The CCSIDR is:

  • A read-only register.

  • Common to the Secure and Non-secure states.

  • Only accessible from PL1 or higher.

Configurations

There is one CCSIDR for each cache size and level of cache. The CSSELR determines which CCSIDR is accessible.

Attributes

See the register summary in Table 4.2.

Figure 4.18 shows the CCSIDR bit assignments.

Figure 4.18. CCSIDR bit assignments

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Table 4.46 shows the CCSIDR bit assignments.

Table 4.46. CCSIDR bit assignments

BitsNameFunction
[31]WT

Indicates support for Write-Through:

0

Cache level does not support Write-Through.

1

Cache level supports Write-Through.

[30]WB

Indicates support for Write-Back:

0

Cache level does not support Write-Back.

1

Cache level supports Write-Back.

[29]RA

Indicates support for Read-Allocation:

0

Cache level does not support Read-Allocation.

1

Cache level supports Read-Allocation.

[28]WA

Indicates support for Write-Allocation:

0

Cache level does not support.

1

Cache level supports Write-Allocation.

[27:13]NumSets[a]

Indicates the number of sets in cache - 1. Therefore, a value of 0 indicates 1 set in the cache. The number of sets does not have to be a power of 2.

[12:3]Associativity[a]

Indicates the associativity of cache - 1. Therefore, a value of 0 indicates an associativity of 1. The associativity does not have to be a power of 2:

0b0000000001

2-ways.

0b0000000011

4-ways.

0b0000000111

8-ways.

[2:0]LineSize[a]

Indicates the (log2 (number of words in cache line)) - 2:

0b001

8 words per line.

0b010

16 words per line.

[a] For more information about encoding, see Table 4.47.


Table 4.47 shows the individual bit field and complete register encodings for the CCSIDR. The CSSELR determines which CCSIDR to select.

Table 4.47. CCSIDR encodings

Cache CSSELRSizeComplete register encodingRegister bit field encoding
WTWBRAWANumSetsAssociativityLineSize
L1 data cache0x08KB0x7003E01A01110x1F0x30x2
16KB0x7007E01A0x3F0x30x2
32KB0x700FE01A0x7F0x30x2
64KB0x701FE01A0xFF0x30x2
L1 instruction cache 0x18KB0x200FE00900100x7F0x10x1
16KB0x201FE0090xFF0x10x1
32KB0x203FE0090x1FF0x10x1
64KB0x207FE0090x3FF0x10x1
L2 cache0x2128KB0x701FE03A01110xFF0x70x2
256KB0x703FE03A0x1FF0x70x2
512KB0x707FE03A0x3FF0x70x2
1024KB0x70FFE03A0x7FF0x70x2
Reserved0x3-0xF---------

To access the CCSIDR, read the CP15 register with:

MRC p15, 1, <Rt>, c0, c0, 0 ; Read Cache Size ID Register
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