A.8.1. APB Interface signals

Table A.17 shows the APB Interface signals.

Table A.17. APB Interface signals

SignalDirectionDescription
PADDRDBG[14:2]InputAPB Address bus bits[14:2]
PADDRDBG31Input

APB address bus bit[31]:

0

Not an external debugger access.

1

External debugger access.

PCLKENDBGInputAPB clock enable
PENABLEDBGInput

Indicates the second and subsequent cycles of an APB transfer.

PRDATADBG[31:0]OutputAPB read data bus
PREADYDBGOutput

APB slave ready. An APB slave can assert PREADYDBG to extend a transfer by inserting wait states.

PSELDBGInputDebug bus access
PSLVERRDBGOutput

APB slave transfer error:

0

No transfer error.

1

Transfer error.

PWDATADBG[31:0]InputAPB write data bus
PWRITEDBGInput

APB read or write signal:

0

Reads from APB.

1

Writes to APB.


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