4.3.16. Instruction Set Attribute Register 1

The ID_ISAR1 characteristics are:

Purpose

Provides information about the instruction set that the processor supports beyond the basic set.

Usage constraints

The ID_ISAR1 is:

  • A read-only register.

  • Common to the Secure and Non-secure states.

  • Only accessible from PL1 or higher.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 4.2.

Figure 4.14 shows the ID_ISAR1 bit assignments.

Figure 4.14. ID_ISAR1 bit assignments

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Table 4.42 shows the ID_ISAR1 bit assignments.

Table 4.42. ID_ISAR1 bit assignments

BitsNameFunction
[31:28]Jazelle_instrs

Indicates the supported Jazelle extension instructions.

0x1

Processor supports BXJ instruction, and the J bit in the PSR.

[27:24]Interwork_instrs

Indicates the supported Interworking instructions.

0x3

Processor supports:

  • BX instruction, and the T bit in the PSR..

  • BLX instruction, and PC loads have BX-like behavior.

  • Data-processing instructions in the ARM instruction set with the PC as the destination and the S bit cleared to 0, have BX-like behavior.

[23:20]Immediate_instrs

Indicates support for data-processing instructions with long immediates.

0x1

Processor supports:

  • MOVT instruction.

  • MOV instruction encodings with zero-extended 16-bit immediates.

  • Thumb ADD and SUB instruction encodings with zero-extended 12-bit immediates, and other ADD, ADR, and SUB encodings cross-referenced by the pseudocode for those encodings.

[19:16]IfThen_instrs

Indicates the supported If-Then instructions in the Thumb instruction set:

0x1

Processor supports the IT instructions, and the IT bits in the PSRs.

[15:12]Extend_instrs

Indicates the supported Extend instructions.

0x2

Processor supports:

  • SXTB, SXTH, UXTB, and UXTH instructions.

  • SXTB16, SXTAB, SXTAB16, SXTAH, UXTB16, UXTAB, UXTAB16, and UXTAH instructions.

[11:8]Except_AR_instrs

Indicates the supported A and R profile exception-handling instructions:

0x1

Processor supports SRS, RFE, and CPS instructions.

[7:4]Except_instrs

Indicates the supported exception-handling instructions in the ARM instruction set:

0x1

Processor supports LDM (exception return), LDM (user registers), and STM (user registers) instructions.

[3:0]Endian_instrs

Indicates the supported Endian instructions:

0x1

Processor supports SETEND instruction, and the E bit in the PSRs.


To access the ID_ISAR1, read the CP15 register with:

MRC p15, 0, <Rt>, c0, c2, 1 ; Read Instruction Set Attribute Register 1
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