8.3.5. Virtual interface control register summary

The virtual interface control registers are management registers. Configuration software on the Cortex-A7 MPCore processor must ensure they are accessible only by a hypervisor, or similar software.

Table 8.11 shows the register map for the virtual interface control registers. The offsets in this table are relative to the virtual interface control registers block base address as shown in Table 8.1.

All the registers in Table 8.11 are word-accessible. Registers not described in this table are RAZ/WI.

Table 8.11. Virtual interface control register summary

OffsetNameTypeResetDescription
0x000GICH_HCRRW0x00000000Hypervisor Control Register, see the ARM Generic Interrupt Controller Architecture Specification
0x004GICH_VTRRO0x90000003VGIC Type Register

0x008

GICH_VMCR

RW

0x004C0000

Virtual Machine Control Register, see the ARM Generic Interrupt Controller Architecture Specification

0x010

GICH_MISR

RO

0x00000000

Maintenance Interrupt Status Register, see the ARM Generic Interrupt Controller Architecture Specification

0x020

GICH_EISR0

RO

0x00000000

End of Interrupt Status Register, see the ARM Generic Interrupt Controller Architecture Specification

0x030

GICH_ELSR0

RO

0x0000000F

Empty List register Status Register, see the ARM Generic Interrupt Controller Architecture Specification

0x0F0GICH_APR0RW0x00000000Active Priorities Register, see the ARM Generic Interrupt Controller Architecture Specification
0x100GICH_LR0RW0x00000000List Register 0, see the ARM Generic Interrupt Controller Architecture Specification
0x104GICH_LR1RW0x00000000List Register 1, see the ARM Generic Interrupt Controller Architecture Specification
0x108GICH_LR2RW0x00000000List Register 2, see the ARM Generic Interrupt Controller Architecture Specification
0x10CGICH_LR3RW0x00000000List Register 3, see the ARM Generic Interrupt Controller Architecture Specification

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