6.6.3. TLB RAM accesses

The Cortex-A7 MPCore processor unified TLB is built from a 2-way set-associative RAM based structure. To read the individual entries into the data registers software must write to the TLB Data Read Operation Register. Table 6.7 shows the write TLB Data Read Operation Register location encoding.

Table 6.7. TLB Data Read Operation Register location encoding

Bit-field of Rd Description
[31] TLB way
[30:8] Unused
[7:0] TLB index

The TLB RAM contains the data for the main TLB, the walk cache, and the Intermediate Physical Address (IPA) cache RAMs. Table 6.8 shows the TLB indexes that determines the format of the TLB RAM accesses.

Table 6.8.  TLB RAM format

TLB index[7:0]Format
0-127Main TLB RAM, see Main TLB RAM
128-159Walk cache RAM, see Walk cache RAM
160-191IPA cache RAM, see IPA cache RAM
192-255Unused

Main TLB RAM

The main TLB RAM uses a 86-bit encoding for the descriptor that is returned in the Data Registers:

Data Register 0[31:0]

TLB Descriptor[31:0].

Data Register 1[31:0]

TLB Descriptor[62:32].

Data Register 2[19:0]

TLB Descriptor[85:64].

Table 6.9 shows the data fields in the TLB descriptor.

Table 6.9.  Main TLB descriptor data fields

Bits NameDescription
[85:84]S2 Level

The stage 2 level that gave this translation:

0b00

No stage 2 translation performed.

0b01

Level 1.

0b10

Level 2.

0b11

Level 3.

[83:82]S1 Size

The stage 1 size that gave this translation:

0b00

4KB.

0b01

64KB.

0b10

1MB (VMSAv7) or 2MB (LPAE).

0b11

16MB (VMSAv7) or 1GB (LPAE).

[81:78]DomainOnly valid if the entry was fetched in VMSAv7 format.
[77:72]Memory Type and shareability

Bits[77:76] are the inner type:

0b00

Non-cacheable.

0b01

Write-Back Write-Allocate.

0b10

Write-Through.

0b11

Device or Strongly Ordered.

If bits[77:76] == 0b11 (Device or Strongly Ordered)

Bit[75] is set if stage-1 translation was overridden by a stage-2 translation.

Bits[74:72] encode the type:

0b010

Device.

0b110

Strongly ordered.

If bits[77:76] != 0b11 (not Device or not Strongly Ordered)

Bits[75:74] are the outer type:

0b00

Non-cacheable.

0b01

Write-Back Write-Allocate.

0b10

Write-Through.

0b11

Write-Back no Write-Allocate.

Bits[73:72] are for shareability:

0b00

Non-shareable.

0b01

Unused.

0b10

Outer Shareable.

0b11

Inner Shareable.

[71]XN2[a]Stage-2 translation Execute Never bit.
[70]

XN1[b]

Stage-1 translation Execute Never bit.
[69]PXN[b]Privileged Execute Never.
[68:41]PAPhysical Address.
[40]NS, descriptor[b]Security state allocated to memory region.
[39:38]HAP[a]Hypervisor access permissions from the stage-2 translation.
[37:35]AP or HYP[b]Access permissions from stage-1 translation and HYP mode flag.
[34]nG[b]Not global.
[33:26]ASIDAddress Space Identifier.
[25:18]VMIDVirtual Machine Identifier.
[17:5]VAVirtual address.
[4]NS, walkSecurity state that the entry was fetched in.
[3:1]Size

This field indicates the VMSA v7 or LPAE TLB RAM size.

VMSA v7:

0b000

4KB.

0b010

64KB.

0b100

1MB.

0b110

16MB.

LPAE:

0b001

4KB.

0b011

64KB.

0b101

2MB.

0b111

1GB.

[0]ValidValid bit, when set to 1 the entry contains valid data.

[a] This is from the Stage 2 page table. See the ARM Architecture Reference Manual for more information.

[b] This is from the Stage 1 page table. See the ARM Architecture Reference Manual for more information.


Walk cache RAM

The walk cache RAM uses a 86-bit encoding. Table 6.10 shows the data fields in the Walk cache descriptor.

Table 6.10. Walk cache descriptor fields

Bits NameDescription
[85:82]Unused-
[81:78]DomainOnly valid if the entry was fetched in VMSAv7 format
[77:48]PAThe physical address of the level 3 (LPAE) or level 2 (VMSAv7) table
[47:41]VAVirtual address
[40]-Unused
[39]NSTableCombined NSTable bits from first and second level stage 1 tables (LPAE) or NS descriptor (VMSAv7)
[38]PXNTableCombined PXNTable bit from first and second level stage 1 tables
[37]XNTableCombined XNTable bit from first and second level stage 1 tables
[36:35]APTableCombined APTable bits from first and second level stage 1 tables
[34]HYPHYP bit, when set to 1 indicates the entry was fetched in HYP mode
[33:26]ASIDIndicates the Address Space Identifier
[25:18]VMIDVirtual Machine Identifier
[17:12]AttrsPhysical attributes of the final level stage 1 table
[11:5]-Unused
[4]NS, walkSecurity state that the entry was fetched in
[3:2]-Unused
[1]LPAE

LPAE bit. Indicates what format the entry was fetched in:

0

VMSAv7 format.

1

LPAE format.

[0]ValidValid bit. When set to 1 the entry contains valid data.

IPA cache RAM

The Intermediate Physical Address (IPA) cache RAM uses a 86-bit encoding. Table 6.10 shows the data fields in the IPA cache descriptor.

Table 6.11. IPA cache descriptor fields

BitsNameDescription
[85:82]MemattrsMemory attributes
[81:59]IPAUnused lower bits, page size dependent, must be zero
[58:31]PAPhysical address
[30]XNExecute Never
[29:28]HAPHypervisor access permissions
[27:26]SHShareability
[25:18]VMIDVirtual Machine Identifier
[17:4]Unused-
[3:1]Size

The size values are:

0b001

4KB.

0b011

64KB.

0b101

2MB.

0b111

1GB.

[0]ValidThe entry contains valid data

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