4.3.15. Instruction Set Attribute Register 0

The ID_ISAR0 characteristics are:


Provides information about the instruction set that the processor supports beyond the basic set.

Usage constraints

The ID_ISAR0 is:

  • A read-only register.

  • Common to the Secure and Non-secure states.

  • Only accessible from PL1 or higher.


Available in all configurations.


See the register summary in Table 4.2.

Figure 4.13 shows the ID_ISAR0 bit assignments.

Figure 4.13. ID_ISAR0 bit assignments

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Table 4.41 shows the ID_ISAR0 bit assignments.

Table 4.41. ID_ISAR0 bit assignments


Reserved, RAZ.


Indicates support for Divide instructions:


Processor supports:

  • SDIV and UDIV in the Thumb instruction set.

  • SDIV and UDIV in the ARM instruction set.


Indicates the supported Debug instructions:


Processor supports BKPT instruction.


Indicates the supported Coprocessor instructions:


None supported, except for separately attributed architectures including CP15, CP14, and Advanced SIMD and VFP.



Indicates the supported combined Compare and Branch instructions in the Thumb instruction set:


Processor supports CBNZ and CBZ instructions.


Indicates the supported bit field instructions:


Processor supports BFC, BFI, SBFX, and UBFX instructions.


Indicates the supported Bit Counting instructions:


Processor supports CLZ instruction.


Indicates the supported Swap instructions in the ARM instruction set:


SWP and SWPB instructions supported fractionally[a].

[a] The SWP instruction only produces a read followed by a write that are not locked on the bus, if enabled in the SCTLR.

See the description of ISAR4:SWP_frac in Instruction Set Attribute Register 4.

To access the ID_ISAR0, read the CP15 register with:

MRC p15, 0, <Rt>, c0, c2, 0 ; Read Instruction Set Attribute Register 0
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