8.3.1. Distributor register summary

The Distributor centralizes all interrupt sources, determines the priority of each interrupt, and for each CPU interface forwards the interrupt with the highest priority to the interface for priority masking and preemption handling.

The Distributor provides a programming interface for:

Table 8.3 shows the register map for the Distributor. The offsets in this table are relative to the Distributor block base address as shown in Table 8.1.

The GICD_IPRIORITYRn, GICD_ITARGETSRn, GICD_CPENDSGIRn, and GICD_SPENDSGIRn registers are byte-accessible and halfword-accessible. All other registers in Table 8.3 are word-accessible. Registers not described in Table 8.3 are RAZ/WI.

Table 8.3. Distributor register summary

Offset

Name

Type

Reset

Full name

0x000

GICD_CTLR

RW

0x00000000[a]

Distributor Control Register, see the ARM Generic Interrupt Controller Architecture Specification

0x004

GICD_TYPER

RO

implementation defined

Interrupt Controller Type Register

0x008

GICD_IIDR

RO

0x0100143B

Distributor Implementer Identification Register

0x080-0x0BC

GICD_IGROUPRn

RW

0x00000000

Interrupt Group Registers, see ARM Generic Interrupt Controller Architecture Specification[b]

0x100

GICD_ISENABLERn

RW[c]

0x0000FFFF[d]

Interrupt Set-Enable Registers, see the ARM Generic Interrupt Controller Architecture Specification

0x104-0x13C

0x00000000

0x180

GICD_ICENABLERn

RW[c]

0x0000FFFF[d]

Interrupt Clear-Enable Registers, see the ARM Generic Interrupt Controller Architecture Specification

0x184-0x1BC

0x00000000

0x200-0x23C

GICD_ISPENDRn

RW

0x00000000

Interrupt Set-Pending Registers, see the ARM Generic Interrupt Controller Architecture Specification

0x280-0x2BC

GICD_ICPENDRn

RW

0x00000000

Interrupt Clear-Pending Registers, see the ARM Generic Interrupt Controller Architecture Specification

0x300-0x33C

GICD_ISACTIVERn

RW

0x00000000

Interrupt Set-Active Registers, see the ARM Generic Interrupt Controller Architecture Specification
0x380-0x3BC

GICD_ICACTIVERn

RW

0x00000000

Interrupt Clear-Active Registers, see the ARM Generic Interrupt Controller Architecture Specification

0x400-0x5FC

GICD_IPRIORITYRn[e]

RW

0x00000000

Interrupt Priority Registers, see ARM Generic Interrupt Controller Architecture Specification

0x800-0x81C

GICD_ITARGETSRn

RO[f]

-

Interrupt Processor Targets Registers, see the ARM Generic Interrupt Controller Architecture Specification

0x820-0x9FC

RW

0x00000000

0xC00

GICD_ICFGRn

RO

0xAAAAAAAA[g]

Interrupt configuration registers

0xC04

RO

0x55540000[g]

0xC08-0xC7C

RW

0x55555555[g]

0xD00

GICD_PPISR

RO

0x00000000

Private Peripheral Interrupt Status Register

0xD04-0xD3C

GICD_SPISRn

RO

0x00000000Shared Peripheral Interrupt Status Registers
0xF00

GICD_SGIR

WO

-Software Generated Interrupt Register, see the ARM Generic Interrupt Controller Architecture Specification
0xF10-0xF1C

GICD_CPENDSGIRn

RW

0x00000000

SGI Clear-Pending Registers, see the ARM Generic Interrupt Controller Architecture Specification

0xF20-0xF2C

GICD_SPENDSGIRn

RW

0x00000000

SGI Set-Pending Registers, see the ARM Generic Interrupt Controller Architecture Specification

0xFD0

GICD_PIDR4

RO

0x00000004

Peripheral ID4 Register, see the ARM Generic Interrupt Controller Architecture Specification

0xFD4

GICD_PIDR5

RO

0x00000000

Peripheral ID5 Register, see the ARM Generic Interrupt Controller Architecture Specification

0xFD8

GICD_PIDR6

RO

0x00000000

Peripheral ID6 Register, see the ARM Generic Interrupt Controller Architecture Specification

0xFDC

GICD_PIDR7

RO

0x00000000

Peripheral ID7 Register, see the ARM Generic Interrupt Controller Architecture Specification

0xFE0

GICD_PIDR0

RO

0x00000090

Peripheral ID0 Register, see the ARM Generic Interrupt Controller Architecture Specification

0xFE4

GICD_PIDR1

RO

0x000000B4

Peripheral ID1 Register, see the ARM Generic Interrupt Controller Architecture Specification

0xFE8

GICD_PIDR2

RO

0x0000002B

Peripheral ID2 Register, see the ARM Generic Interrupt Controller Architecture Specification

0xFEC

GICD_PIDR3

RO

0x00000000

Peripheral ID3 Register, see the ARM Generic Interrupt Controller Architecture Specification

0xFF0

GICD_CIDR0

RO

0x0000000D

Component ID0 Register, see the ARM Generic Interrupt Controller Architecture Specification

0xFF4

GICD_CIDR1

RO

0x000000F0Component ID1 Register, see the ARM Generic Interrupt Controller Architecture Specification

0xFF8

GICD_CIDR2

RO

0x00000005

Component ID2 Register, see the ARM Generic Interrupt Controller Architecture Specification

0xFFC

GICD_CIDR3

RO

0x000000B1

Component ID3 Register, see the ARM Generic Interrupt Controller Architecture Specification

[a] You cannot modify the EnableGrp0 bit if CFGSDISABLE is asserted.

[b] This register is only accessible from a Secure access.

[c] Writes to bits corresponding to the SGIs are ignored.

[d] The reset value for the register that contains the SGI and PPI interrupts is 0x0000FFFF because SGIs are always enabled. However, SGIs are Group 0 on reset, so the reset value for Non-secure reads is 0x00000000.

[e] Writing to the GICD_IPRIORITYR does not affect the priority of an active interrupt.

[f] The register that contains the SGI and PPI interrupts is read-only and the value is implementation defined. For Cortex-A7 configurations with only one processor, these registers are RAZ/WI.

[g] The reset value for the register that contains the SGI interrupts is 0xAAAAAAAA. The reset value for the register that contains the PPI interrupts is 0x55540000. The reset value for the registers that contain the SPI interrupts is 0x55555555.


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