4.2.8. c7 registers

Table 4.8 shows the 32-bit wide system control registers you can access when CRn is c7.

Table 4.8. c7 register summary

CRnOp1CRmOp2NameResetDescription
c70c04NOPUNK

No Operation, see the ARM Architecture Reference Manual

c10ICIALLUISUNK

Instruction cache invalidate all to PoU[a] Inner Shareable, see the ARM Architecture Reference Manual

6BPIALLISUNK

Branch predictor invalidate all Inner Shareable, see the ARM Architecture Reference Manual

c40PAR

UNK

Physical Address Register
c50ICIALLUUNK

Instruction cache invalidate all to PoU, see the ARM Architecture Reference Manual

1ICIMVAUUNK

Instruction cache invalidate by MVA to PoU, see the ARM Architecture Reference Manual

4CP15ISBUNK

Instruction Synchronization Barrier operation, see the ARM Architecture Reference Manual

6BPIALLUNK

Branch predictor invalidate all, see the ARM Architecture Reference Manual

7BPIMVAUNK

Branch predictor invalidate by MVA, see the ARM Architecture Reference Manual

c61DCIMVAC[b]UNK

Data cache invalidate by MVA to PoC[c], see the ARM Architecture Reference Manual

2DCISW[d]UNK

Data cache invalidate line by set/way, see the ARM Architecture Reference Manual

c80ATS1CPRUNK

Stage 1 current state PL1 read, see the ARM Architecture Reference Manual

1ATS1CPWUNK

Stage 1 current state PL1 write, see the ARM Architecture Reference Manual

2ATS1CURUNK

Stage 1 current state unprivileged (PL0) read, see the ARM Architecture Reference Manual

3ATS1CUWUNK

Stage 1 current state unprivileged (PL0) write, see the ARM Architecture Reference Manual

4ATS12NSOPRUNK

Stages 1 and 2 Non-secure PL1 read, see the ARM Architecture Reference Manual

5ATS12NSOPWUNK

Stages 1 and 2 Non-secure PL1 write, see the ARM Architecture Reference Manual

6ATS12NSOURUNK

Stages 1 and 2 Non-secure unprivileged (PL0) read, see the ARM Architecture Reference Manual

7ATS12NSOUWUNK

Stages 1 and 2 Non-secure unprivileged (PL0) write, see the ARM Architecture Reference Manual

c101DCCMVACUNK

Data cache clean line by MVA to PoC, see the ARM Architecture Reference Manual

c70c102DCCSWUNK

Data cache clean line by set/way, see the ARM Architecture Reference Manual

4CP15DSBUNK

Data Synchronization Barrier operation, see the ARM Architecture Reference Manual

5CP15DMBUNK

Data Memory Barrier operation, see the ARM Architecture Reference Manual

c111DCCMVAUUNK

Clean data cache line by MVA to PoU, see the ARM Architecture Reference Manual

c131NOPUNK

No Operation, see the ARM Architecture Reference Manual

c141DCCIMVACUNK

Data cache clean and invalidate line by MVA to PoC, see the ARM Architecture Reference Manual

2DCCISWUNK

Data cache clean and invalidate line by set/way, see the ARM Architecture Reference Manual

4c80ATS1HRUNK

Add translation stage 1 Hyp mode read, see the ARM Architecture Reference Manual

1ATS1HWUNK

Add translation stage 1 Hyp mode write, see the ARM Architecture Reference Manual

[a] PoU = Point of Unification. If BROADCASTINNER is LOW, the PoU is the L1 data cache. If BROADCASTINNER is HIGH then the PoU is outside of the processor and is dependent on the external memory system..

[b] DCIMVAC is upgraded to DCCIMVAC for the individual processor that the DCIMVAC is executed on. Additionally, if the DCIMVAC is executed from a Non-secure state other than Hyp mode without second state write permissions then the DCIMVAC is upgraded to DCCIMVAC when broadcast to other processors or broadcast on the ACE interface.

[c] PoC = Point of Coherence. The PoC is always outside of the processor and is dependent on the external memory system.

[d] DCISW is upgraded to DCCISW when executed in a Non-secure PL1 mode if HCR.SWIO is set to 1.


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