4.3.13. Memory Model Feature Register 2

The ID_MMFR2 characteristics are:

Purpose

Provides information about the memory model and memory management support of the processor.

Usage constraints

The ID_MMFR2 is:

  • A read-only register.

  • Common to the Secure and Non-secure states.

  • Only accessible from PL1 or higher.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 4.2.

Figure 4.11 shows the ID_MMFR2 bit assignments.

Figure 4.11. ID_MMFR2 bit assignments

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Table 4.39 shows the ID_MMFR2 bit assignments.

Table 4.39. ID_MMFR2 bit assignments

BitsNameFunction
[31:28]HW Access flag

Indicates support for Hardware Access flag:

0x0

Not supported.

[27:24]WFI stall

Indicates support for Wait For Interrupt (WFI) stalling:

0x1

Processor supports WFI stalling.

[23:20]Memory barrier

Indicates the supported CP15 memory barrier operations.

0x2

Processor supports:

  • Data Synchronization Barrier (DSB).

  • Instruction Synchronization Barrier (ISB).

  • Data Memory Barrier (DMB).

[19:16]Unified TLB

Indicates the supported TLB maintenance operations, for a unified TLB implementation.

0x4

Processor supports:

  • Invalidate all entries in the TLB.

  • Invalidate TLB entry by MVA.

  • Invalidate TLB entries by ASID match.

  • Invalidate TLB entries by MVA All ASID.

  • Invalidate unified Hyp TLB entry by MVA.

  • Invalidate entire Non-secure Non-Hyp unified TLB.

  • Invalidate entire Hyp unified TLB.

[15:12]Harvard TLB

Indicates the supported TLB maintenance operations, for a Harvard TLB implementation:

0x0

Not supported.

[11:8]L1 Harvard range

Indicates the supported L1 cache maintenance range operations, for a Harvard cache implementation:

0x0

Not supported.

[7:4]L1 Harvard background prefetch

Indicates the supported L1 cache background prefetch operations, for a Harvard cache implementation:

0x0

Not supported.

[3:0]L1 Harvard foreground prefetch

Indicates the supported L1 cache foreground prefetch operations, for a Harvard cache implementation:

0x0

Not supported.


To access the ID_MMFR2, read the CP15 register with:

MRC p15, 0, <Rt>, c0, c1, 6; Read Memory Model Feature Register 2
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