4.3.17. Instruction Set Attribute Register 2

The ID_ISAR2 characteristics are:

Purpose

Provides information about the instruction set that the processor supports beyond the basic set.

Usage constraints

The ID_ISAR2 is:

  • A read-only register.

  • Common to the Secure and Non-secure states.

  • Only accessible from PL1 or higher.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 4.2.

Figure 4.15 shows the ID_ISAR2 bit assignments.

Figure 4.15. ID_ISAR2 bit assignments

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Table 4.43 shows the ID_ISAR2 bit assignments.

Table 4.43. ID_ISAR2 bit assignments

BitsNameFunction
[31:28]Reversal_instrs

Indicates the supported Reversal instructions:

0x2

Processor supports REV, REV16, REVSH, and RBIT instructions.

[27:24]PSR_instrs

Indicates the supported PSR instructions:

0x1

Processor supports MRS and MSR instructions, and the exception return forms of data-processing instructions.

Note

The exception return forms of the data-processing instructions are:

  • In the ARM instruction set, data-processing instructions with the PC as the destination and the S bit set. These instructions might be affected by the ISAR4.WithShifts attribute.

  • In the Thumb instruction set, the SUBS PC, LR, #N instruction.

[23:20]MultU_instrs

Indicates the supported advanced unsigned Multiply instructions:

0x2

Processor supports UMULL, UMLAL, and UMAAL instructions.

[19:16]MultS_instrs

Indicates the supported advanced signed Multiply instructions.

0x3

Processor supports:

  • SMULL and SMLAL instructions.

  • SMLABB, SMLABT, SMLALBB,SMLALBT, SMLALTB, SMLALTT, SMLATB, SMLATT, SMLAWB, SMLAWT, SMULBB, SMULBT, SMULTB, SMULTT, SMULWB, SMULWT instructions, and the Q bit in the PSRs.

  • SMLAD, SMLADX, SMLALD, SMLALDX, SMLSD, SMLSDX, SMLSLD, SMLSLDX, SMMLA, SMMLAR, SMMLS, SMMLSR, SMMUL, SMMULR, SMUAD, SMUADX, SMUSD, and SMUSDX instructions.

[15:12]Mult_instrs

Indicates the supported additional Multiply instructions:

0x2

Processor supports MUL, MLA, and MLS instructions.

[11:8]MultiAccessInt_instrs

Indicates support for interruptible multi-access instructions:

0x0

None supported. This means that the processor does not support interruptible LDM and STM instructions.

[7:4]MemHint_instrs

Indicates the supported memory hint instructions:

0x4

Processor supports PLD, PLI (NOP), and PLDW instructions.

[3:0]LoadStore_instrs

Indicates the supported additional load/store instructions:

0x1

Processor supports LDRD and STRD instructions.


To access the ID_ISAR2, read the CP15 register with:

MRC p15, 0, <Rt>, c0, c2, 2 ; Read Instruction Set Attribute Register 2
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