4.2.3. c2 registers

Table 4.4 shows the 32-bit wide system control registers you can access when CRn is c2.

Table 4.4. c2 register summary

CRnOp1CRmOp2NameResetDescription
c20c00TTBR0UNKTranslation Table Base Register 0, see the ARM Architecture Reference Manual
1TTBR1UNKTranslation Table Base Register 1, see the ARM Architecture Reference Manual
2TTBCR

0x00000000[a]

Translation Table Base Control Register, see the ARM Architecture Reference Manual
4c02HTCRUNK

Hyp Translation Control Register

c12VTCRUNK

Virtualization Translation Control Register, see the ARM Architecture Reference Manual

[a] The reset value is 0x00000000 for the Secure copy of the register. The reset value for the EAE bit of the Non-secure copy of the register is 0x0. You must program the Non-secure copy of the register with the required initial value, as part of the processor boot sequence.


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