4.2.10. c9 registers

Table 4.10 shows the 32-bit wide system control registers you can access when CRn is c9.

Table 4.10. c9 register summary

CRnOp1CRmOp2NameResetDescription
c90c120PMCR0x41072000

Performance Monitor Control Register

1PMNCNTENSETUNK

Count Enable Set Register, see the ARM Architecture Reference Manual

2PMNCNTENCLRUNK

Count Enable Clear Register, see the ARM Architecture Reference Manual

3PMOVSRUNK

Overflow Flag Status Register, see the ARM Architecture Reference Manual

4PMSWINCUNK

Software Increment Register, see the ARM Architecture Reference Manual

5PMSELRUNK

Event Counter Selection Register, see the ARM Architecture Reference Manual

6PMCEID00x3FFF0F3F

Common Event Identification Register 0, see the ARM Architecture Reference Manual

7PMCEID10x00000000Common Event Identification Register 1, see the ARM Architecture Reference Manual
c130PMCCNTRUNK

Cycle Count Register, see the ARM Architecture Reference Manual

1

PMXEVTYPER

UNK

Event Type Selection Register, see the ARM Architecture Reference Manual

2PMXEVCNTRUNK

Event Count Register, see the ARM Architecture Reference Manual

c140PMUSERENR0x00000000

User Enable Register, see the ARM Architecture Reference Manual

c90c141PMINTENSETUNK

Interrupt Enable Set Register, see the ARM Architecture Reference Manual

2PMINTENCLRUNK

Interrupt Enable Clear Register, see the ARM Architecture Reference Manual

3PMOVSSETUNK

Performance Monitor Overflow Flag Status Set Register, see the ARM Architecture Reference Manual

1c02L2CTLR0x00000000[a]

L2 Control Register

3L2ECTLR0x00000000L2 Extended Control Register

[a] The reset value depends on the processor configuration.


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