4.3.34. Non-Secure Access Control Register

The NSACR characteristics are:

Purpose

Defines the Non-secure access permission to coprocessors CP10 andCP11, and to the following bits:

Usage constraints

The NSACR is only accessible from PL1 or higher, with access rights that depend on the mode and security state:

  • Read/write in Secure PL1 modes.

  • Read-only in Non-secure PL1 and PL2 modes.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 4.3.

Figure 4.30 shows the NSACR bit assignments.

Figure 4.30. NSACR bit assignments

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Table 4.63 shows the NSACR bit assignments.

Table 4.63. NSACR bit assignments

BitsNameFunction
[31:20]-

Reserved, UNK/SBZP.

[19]-

Reserved, RAZ/WI.

[18]NS_SMP

Determines if the SMP bit of the Auxiliary Control Register (ACTLR) is writable in Non-secure state:

0

A write to ACTLR in Non-secure state is write-ignored. This is the reset value.

1

A write to ACTLR in Non-secure state can modify the value of the SMP bit. Other bits in the ACTLR are write-ignored.

[17]NS_L2ERR

NS_L2ERR Determines if the L2 AXI asynchronous error bit of the L2 Extended Control Register (L2ECTLR), are writable in Non-secure state:

0

A write to L2ECTLR in Non-secure state is ignored. This is the reset value.

1

A write to L2ECTLR in Non-secure state can modify the value of the L2 AXI asynchronous error bit. Other bits in the L2ECTLR are write-ignored.

[16]-

Reserved, RAZ/WI.

[15]NSASEDIS

Disable Non-secure Advanced SIMD functionality:

0

This bit has no effect on the ability to write CPACR.ASEDIS, this is the reset value.

1

When executing in Non-secure state, the CPACR.ASEDIS bit has a fixed value of 1 and writes to it are ignored.

If FPU is implemented and Advanced SIMD is not implemented, this bit is RAO/WI.

If FPU and Advanced SIMD are not implemented, this bit is UNK/SBZP.

[14]NSD32DIS

Disable the Non-secure use of D16-D31 of the VFP register file:

0

This bit has no effect on the ability to write CPACR. D32DIS. This is the reset value.

1

The CPACR.D32DIS bit when executing in Non-secure state has a fixed value of 1 and writes to it are ignored.

If FPU is implemented and Advanced SIMD is implemented, ARM deprecates writing a value that is not zero to this bit.

If FPU is implemented and Advanced SIMD is not implemented, this bit is RAO/WI.

If FPU and Advanced SIMD are not implemented, this bit is UNK/SBZP.

[13:12]-

Reserved, RAZ/WI.

[11]cp11

Non-secure access to coprocessor 11 enable:

0

Secure access only. Any attempt to access coprocessor 11 in Non-secure state results in an Undefined Instruction exception. If the processor is in Non-secure state, the corresponding bits in the CPACR ignore writes and read as 0b00, access denied. This is the reset value.

1

Secure or Non-secure access.

If FPU and Advanced SIMD are not implemented, this bit is RAZ/WI.

[10]cp10

Non-secure access to coprocessor 10 enable:

0

Secure access only. Any attempt to access coprocessor 10 in Non-secure state results in an Undefined Instruction exception. If the processor is in Non-secure state, the corresponding bits in the CPACR ignore writes and read as 0b00, access denied. This is the reset value.

1

Secure or Non-secure access.

If FPU and Advanced SIMD are not implemented, this bit is RAZ/WI.

[9:0]-

Reserved, RAZ/WI.


Note

If the values of the cp11 and cp10 fields are not the same, the behavior is UNPREDICTABLE.

To access the NSACR, read or write the CP15 register with:

MRC p15, 0, <Rt>, c1, c1, 2 ; Read Non-Secure Access Control Register data
MCR p15, 0, <Rt>, c1, c1, 2 ; Write Non-Secure Access Control Register data
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