4.3.5. Multiprocessor Affinity Register

The MPIDR characteristics are:

Purpose

Provides an additional processor identification mechanism for scheduling purposes in a multiprocessor system.

Usage constraints

The MPIDR is:

  • A read-only register.

  • Common to the Secure and Non-secure states.

  • Only accessible from PL1 or higher.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 4.2.

Figure 4.4 shows the MPIDR bit assignments.

Figure 4.4. MPIDR bit assignments

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Table 4.32 shows the MPIDR bit assignments.

Table 4.32. MPIDR bit assignments

BitsNameFunction
[31]-

Indicates that the processor implements the Multiprocessing Extensions register format:

0x1

ARMv7 multi-processor format

[30]U

Indicates a Uniprocessor system, as distinct from processor 0 in a multiprocessor system:

0x0

Processor is part of a multiprocessor system.

[29:25]-Reserved, RAZ.
[24]MT

Indicates whether the lowest level of affinity consists of logical processors that are implemented using a multi-threading type approach.

0x0

Processors are not implemented using a multi-threading approach.

[23:12]-

Reserved, RAZ.

[11:8]Cluster ID

Indicates the value read in the CLUSTERID configuration pin. It identifies each Cortex-A7 MPCore processor in a system with more than one processor present. That is, there are other processors in the multiprocessor system that might not be Cortex-A7 MPCore processors.

[7:2]-

Reserved, RAZ.

[1:0]CPU ID

Indicates the processor number in the Cortex-A7 MPCore processor. For:

  • One processor, the CPU ID is 0x0.

  • Two processors, the CPU IDs are 0x0 and 0x1.

  • Three processors, the CPU IDs are 0x0, 0x1, and 0x2.

  • Four processors, the CPU IDs are 0x0, 0x1, 0x2, and 0x3.

.


To access the MPIDR, read the CP15 registers with:

MRC p15, 0, <Rt>, c0, c0, 5; Read Multiprocessor Affinity Register
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