4.3.19. Instruction Set Attribute Register 4

The ID_ISAR4 characteristics are:


Provides information about the instruction set that the processor supports beyond the basic set.

Usage constraints

The ID_ISAR4 is:

  • A read-only register.

  • Common to the Secure and Non-secure states.

  • Only accessible from PL1 or higher.


Available in all configurations.


See the register summary in Table 4.2.

Figure 4.17 shows the ID_ISAR4 bit assignments.

Figure 4.17. ID_ISAR4 bit assignments

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Table 4.45 shows the ID_ISAR4 bit assignments.

Table 4.45. ID_ISAR4 bit assignments


Indicates support for the memory system locking the bus for SWP or SWPB instructions:


Processor supports SWP and SWPB instruction but only in a uniprocessor context. SWP and SWPB do not guarantee whether memory accesses from other masters can come between the load memory access and the store memory access of the SWP or SWPB instruction.


Indicates the supported M profile instructions to modify the PSRs:


None supported.


This field is used with the SynchPrim_instrs field of ID_ISAR3 to indicate the supported Synchronization Primitive instructions:


Processor supports:

  • LDREX and STREX instructions.

  • CLREX, LDREXB, LDREXH, STREXB, and STREXH instructions.

  • LDREXD and STREXD instructions.


Indicates the supported Barrier instructions in the ARM and Thumb instruction sets:


Processor supports DMB, DSB, and ISB barrier instructions.


Indicates the supported SMC instructions:


Processor supports SMC instruction.


Indicates support for Write-Back addressing modes:


Processor supports all Write-Back addressing modes defined in ARMv7 architecture.


Indicates support for instructions with shifts.


Processor supports:

  • Shifts of loads and stores over the range LSL 0-3.

  • Constant shift options, both on load/store and other instructions.

  • Register-controlled shift options.


Indicates the supported unprivileged instructions.


Processor supports:

  • LDRBT, LDRT, STRBT, and STRT instructions.

  • LDRHT, LDRSBT, LDRSHT, and STRHT instructions.

To access the ID_ISAR4, read the CP15 register with:

MRC p15, 0, <Rt>, c0, c2, 4 ; Read Instruction Set Attribute Register 4
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