9.2. Generic timer functional description

The Cortex-A7 MPCore processor provides a set of four timers for each processor in the cluster.

The counter value is distributed to the processor with a synchronous binary encoded 64-bit bus, CNTVALUEB[63:0].

Table A.4 shows the signals that are the external interrupt output pins.

Copyright © 2011-2013 ARM. All rights reserved.ARM DDI 0464F