A.8.4. ETM interface signals

Table A.20 shows the ETM interface signals.

Table A.20. ETM interface signals

ETMICTLx[20:0][a]OutputETM instruction control bus
ETMIAx[31:1]OutputETM instruction address
ETMDCTLx[10:0]OutputETM data control bus
ETMDAx[31:0]OutputETM data address
ETMDDx[63:0]OutputETM data write data value
ETMCIDx[31:0]OutputCurrent processor Context ID
ETMVMIDx[7:0]OutputCurrent processor Virtual Machine ID
ETMWFXPENDINGxOutputProcessor is attempting to enter WFI or WFE low-power state
ETMPWRUPxInputPower up processor ETM interface
ETMEXTOUTx[1:0]InputETM external event to be monitored
PMUEVENTx[29:0]OutputPerformance monitor unit output.

[a] x is 0, 1, 2, or 3 to reference processor 0-3.

Copyright © 2011-2013 ARM. All rights reserved.ARM DDI 0464F