A.7.5. Write data response channel signals

Table A.10 shows the write data response channel signals for the ACE master interface.

Table A.10. Write data response channel signals

SignalDirectionDescription
BIDM[4:0]InputResponse ID
BREADYMOutputResponse ready
BRESPM[1:0]InputWrite response
BVALIDMInputResponse valid

Copyright © 2011-2013 ARM. All rights reserved.ARM DDI 0464F
Non-ConfidentialID051113