4.3.27. System Control Register

The SCTLR characteristics are:

Purpose

Provides the top level control of the system, including its memory system.

Usage constraints

The SCTLR is:

  • A read/write register.

  • Banked for Secure and Non-secure states for all implemented bits.

  • Only accessible from PL1 or higher.

  • Has write access to the Secure copy of the register disabled when the CP15SDISABLE signal is asserted HIGH. Attempts to write to this register in Secure PL1 modes when CP15SDISABLE is HIGH result in an Undefined Instruction exception.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 4.3.

Figure 4.23 shows the SCTLR bit assignments.

Figure 4.23. SCTLR bit assignments

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Table 4.52 shows the SCTLR bit assignments.

Table 4.52. SCTLR bit assignments

BitsNameFunction
[31]-

Reserved, UNK/SBZP.

[30]TE

Thumb Exception enable. This bit controls whether exceptions are taken in ARM or Thumb state:

0

Exceptions, including reset, taken in ARM state.

1

Exceptions, including reset, taken in Thumb state.

The primary input CFGTE defines the reset value of the TE bit.

[29]AFE

Access flag enable bit. This bit enables use of the AP[0] bit in the translation table descriptors as the Access flag.

0

In the translation table descriptors, AP[0] is an access permissions bit. The full range of access permissions is supported. No Access flag is implemented. This is the reset value.

1

In the translation table descriptors, AP[0] is the Access flag. Only the simplified model for access permissions is supported.

[28]TRE

TEX remap enable bit. This bit enables remapping of the TEX[2:1] bits for use as two translation table bits that can be managed by the operating system. Enabling this remapping also changes the scheme used to describe the memory region attributes in the VMSA:

0

TEX remap disabled. TEX[2:0] are used, with the C and B bits, to describe the memory region attributes. This is the reset value.

1

TEX remap enabled. TEX[2:1] are reassigned for use as bits managed by the operating system. The TEX[0], C and B bits are used to describe the memory region attributes, with the MMU remap registers.

[27:26]-

Reserved, RAZ/WI.

[25]EE

Exception Endianness bit. The value of this bit defines the value of the CPSR.E bit on entry to an exception vector, including reset. This value also indicates the endianness of the translation table data for translation table lookups:

0

Little endian.

1

Big endian.

The primary input CFGEND defines the reset value of the EE bit.

[24]-

Reserved, RAZ/WI.

[23:22]-

Reserved, RAO/SBOP.

[21]-

Reserved, RAZ/WI.

[20]UWXN

Unprivileged write permission implies PL1 Execute Never (XN). This bit can be used to require all memory regions with unprivileged write permissions to be treated as XN for accesses from software executing at PL1.

0

Regions with unprivileged write permission are not forced to be XN, this is the reset value.

1

Regions with unprivileged write permission are forced to be XN for accesses from software executing at PL1

[19]WXN

Write permission implies Execute Never (XN). This bit can be used to require all memory regions with write permissions to be treated as XN.

0

Regions with write permission are not forced to be XN, this is the reset value.

1

Regions with write permissions are forced to be XN.

[18]-

Reserved, RAO/SBOP.

[17]-

Reserved, RAZ/WI.

[16]-

Reserved, RAO/SBOP.

[15]-

Reserved, RAZ/SBZP.

[14]-

Reserved, RAZ/WI.

[13]V

Vectors bit. This bit selects the base address of the exception vectors:

0

Normal exception vectors, base address 0x00000000. Software can remap this base address using the VBAR.

1

High exception vectors, base address 0xFFFF0000. This base address is never remapped.

The primary input VINITHI defines the reset value of the V bit.

[12]I

Instruction cache enable bit. This is a global enable bit for instruction caches:

0

Instruction caches disabled, this is the reset value.

1

Instruction caches enabled.

[11]ZRAO/WI. Branch prediction enable bit. Branch prediction, also called program flow prediction, is always enabled when the MMU is enabled.
[10]SW

SWP and SWPB enable bit. This bit enables the use of SWP and SWPB instructions:

0

SWP and SWPB are undefined. This is the reset value.

1

SWP and SWPB perform normally[a].

[9:7]-

Reserved, RAZ/SBZP.

[6:3]-

Reserved, RAO/SBOP.

[2]C

Cache enable bit. This is a global enable bit for data and unified caches:

0

Data and unified caches disabled, this is the reset value.

1

Data and unified caches enabled.

The caches are disabled when ACTLR.SMP is set to 0 regardless of the value of the cache enable bit.

[1]A

Alignment bit. This is the enable bit for Alignment fault checking:

0

Alignment fault checking disabled, this is the reset value.

1

Alignment fault checking enabled.

[0]M

Address translation enable bit. This is a global enable bit for the MMU stage 1 address translation:

0

Address translation disabled, this is the reset value.

1

Address translation enabled.

[a] SWP and SWPB do not cause bus locked transfers.


To access the SCTLR, read or write the CP15 register with:

MRC p15, 0, <Rt>, c1, c0, 0 ; Read System Control Register
MCR p15, 0, <Rt>, c1, c0, 0 ; Write System Control Register
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