10.4.21. Debug Device ID Register

The DBGDEVID characteristics are:

Purpose

Extends the DBGDIDR by describing other features of the debug implementation.

Usage constraints

Use in conjunction with DBGDIDR to find the features of the debug implementation. See Table 10.2.

Configurations

DBGDEVID is an optional register.

Attributes

See the register summary in Table 10.1.

Figure 10.24 shows the DBGDEVID bit assignments.

Figure 10.24. DBGDEVID bit assignments

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Table 10.23 shows the DBGDEVID bit assignments.

Table 10.23. DBGDEVID bit assignments

BitsNameFunction
[31:28]CIDMask

Indicates the level of support for the Context ID matching breakpoint masking capability:

0b0000

Context ID masking is not implemented.

[27:24]AuxRegs

Specifies support for the Debug External Auxiliary Control Register. See Debug External Auxiliary Control Register:

0b0001

The processor supports Debug External Auxiliary Control Register.

[23:20]DoubleLock

Specifies support for the Debug OS Double Lock Register:

0b0001

The processor supports Debug OS Double-lock Register.

[19:16]VirExtns

Specifies the implementation of the Virtualization Extensions to the Debug architecture:

0b0001

The processor implements the Virtualization Extensions to the Debug architecture.

[15:12]VectorCatch

Defines the form of the vector catch event implemented:

0b0000

The processor implements address matching form of vector catch.

[11:8]BPAddrMask

Indicates the level of support for the Immediate Virtual Address (IVA) matching breakpoint masking capability:

0b1111

Breakpoint address masking not implemented. DBGBCRn[28:24] are UNK/SBZP.

[7:4]WPAddrMask

Indicates the level of support for the DVA matching watchpoint masking capability:

0b0001

Watchpoint address mask implemented.

[3:0]PCSample

Indicates the level of support for Program Counter sampling using debug registers 40, 41, and 42:

0b0011

DBGPCSR, DBGCIDSR and DBGVIDSR are implemented as debug registers 40, 41, and 42.


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