10.4.4. Debug External Auxiliary Control Register

The DBGEACR characteristics are:


Provides implementation-defined configuration and control options.

Usage constraints

The DBGEACR is accessible when the CPU is powered off. The DBGEACR is not accessible from the CP14 interface.


Available in all configurations.


See the register summary in Table 10.1.

Figure 10.5 shows the DBGEACR bit assignments.

Figure 10.5. DBGEACR bit assignments

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Table 10.5 shows the DBGEACR bit assignments.

Table 10.5. DBGEACR bit assignments


Reserved, RAZ/WI.

[3]Core debug reset status

Read-only status bit that reflects the current reset state of the debug logic in the CPU power domain:


Debug logic in CPU power domain is not in reset state.


Debug logic in CPU power domain is currently in reset state.


Reserved, RAZ/WI.

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