8.3.8. Virtual CPU interface register description

This section only describes the registers whose implementation is specific to the Cortex-A7 MPCore processor. All other registers are described in the ARM Generic Interrupt Controller Architecture Specification.

VM Active Priority Register

The GICV_APR0 characteristics are:

Purpose

For software compatibility, this register is present in the virtual CPU interface. However, in virtualized system, it is not used in the preserving and restoring state.

Usage constraints.

Reading the content of this register and then writing the same values must not change any state because there is no requirement to preserve and restore state during a power down.

Configurations

Available if the GIC is implemented.

Attributes

See the register summary in Table 8.13.

The Cortex-A7 MPCore processor implements the GICV_APR0 as an alias of GICH_APR.

VM CPU Interface Identification Register

The GICV_IIDR characteristics are:

Purpose

Provides information about the implementer and revision of the Virtual CPU interface.

Usage constraints

There are no usage constraints.

Configurations

Available if the GIC is implemented.

Attributes

See the register summary in Table 8.13.

The bit assignments for the VM CPU Interface Identification Register are identical to the corresponding register in the CPU Interface, see CPU Interface Identification Register.

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