8.3.6. Virtual Interface Control Register description

This section only describes registers whose implementation is specific to the Cortex-A7 MPCore processor. All other registers are described in the ARM Generic Interrupt Controller Architecture Specification.

VGIC Type Register

The GICH_VTR characteristics are:


Holds information about the number of priority bits, number of pre-emption bits, and number of List Registers implemented.

Usage constraints

There are no usage constraints.


Available if the GIC is implemented.


See the register summary in Table 8.11.

Figure 8.7 shows the GICH_VTR bit assignments.

Figure 8.7. GICH_VTR bit assignments

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Table 8.12 shows the GICH_VTR bit assignments.

Table 8.12. GICH_VTR bit assignments

BitsName Function
[31:29] PRIbits

Indicates the number of priority bits implemented, minus one:


5 bits of priority and 32 priority levels.


Indicates the number of pre-emption bits implemented, minus one:


5 bits of pre-emption and 32 pre-emption levels.

[25:6]-Reserved, RAZ.

Indicates the number of implemented List Registers, minus one:


4 List Registers.

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