8.3.2. Distributor register descriptions

This section only describes registers whose implementation is specific to the Cortex-A7 MPCore processor. All other registers are described in the ARM Generic Interrupt Controller Architecture Specification.

Interrupt Controller Type Register

The GICD_TYPER characteristics are:

Purpose

Provides information about the configuration of the integrated GIC. It indicates:

  • Whether the GIC implements the Security Extensions.

  • The maximum number of interrupt IDs that the GIC supports.

  • The maximum number of processor interfaces implemented.

  • If the GIC implements the Security Extensions, the maximum number of implemented Lockable Shared Peripheral Interrupts (LSPIs).

Usage constraints

There are no usage constraints.

Configurations

Available if the GIC is implemented.

Attributes

See the register summary in Table 8.3.

Figure 8.1 shows the GICD_TYPER bit assignments.

Figure 8.1. GICD_TYPER bit assignments

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Table 8.4 shows the GICD_TYPER bit assignments.

Table 8.4. GICD_TYPER bit assignments

Bits Name Function
[31:16] - Reserved, RAZ.
[15:11] LSPI

Returns the number of Lockable Shared Peripheral Interrupts (LSPIs) that the Interrupt Controller contains:

0b11111

31 LSPIs, these are the interrupts of IDs 32-62.

When CFGSDISABLE is asserted, the GIC prevents writes to any register locations that control the operating state of an LSPI.

[10] SecurityExtn Indicates whether the GIC implements the Security Extensions. This bit always returns a value of 1, indicating that the Security Extensions are implemented.
[9:8]-Reserved, RAZ.
[7:5]CPUNumber

Indicates the number of implemented processors:

0b000

The Cortex-A7 MPCore configuration contains one processor.

0b001

The Cortex-A7 MPCore configuration contains two processors.

0b010

The Cortex-A7 MPCore configuration contains three processors.

0b011

The Cortex-A7 MPCore configuration contains four processors.

All other values are reserved for future expansions.

[4:0] ITLinesNumber

Indicates the number of interrupts that the GIC supports:

0b00000

Up to 32 interrupts[a], no external interrupt lines.

0b00001

Up to 64 interrupts, 32 external interrupt lines.

0b00010

Up to 96 interrupts, 64 external interrupt lines.

.

.

.

0b01111

Up to 512 interrupts, 480 external interrupt lines.

All other values are reserved for future expansions.

[a] The Distributor always uses interrupts of IDs 0 to 31 to control any SGIs and PPIs that the GIC might contain.


Distributor Implementer Identification Register

The GICD_IIDR characteristics are:

Purpose

Provides information about the implementer and revision of the Distributor.

Usage constraints

There are no usage constraints.

Configurations

Available if the GIC is implemented.

Attributes

See the register summary in Table 8.3.

Figure 8.2 shows the GICD_IIDR bit assignments.

Figure 8.2. GICD_IIDR bit assignments

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Table 8.5 shows the GICD_IIDR bit assignments.

Table 8.5. GICD_IIDR bit assignments

Bits Name Description
[31:24] ProductID

Indicates the product ID of the GIC:

0x01

Cortex-A7.

[23:20] - Reserved, RAZ.
[19:16] Variant

Indicates the major revision number of the GIC:

0x0

Variant number.

[15:12] Revision

Indicates the minor revision number of the GIC:

0x1

Revision number.

[11:0] Implementer

Indicates the implementer:

0x43B

ARM implementation.


Interrupt configuration registers

The GICD_ICFGR provides a 2-bit field that describes the configuration for each interrupt that the GIC supports.

The options for each bit-pair depend on the interrupt type as follows:

SGI

The bits are read-only and a bit-pair always reads as b10 because SGIs are edge-triggered.

PPI

The bits are read-only and a bit-pair always reads as b01 because the PPIs are implemented as level-sensitive.

SPI

The Least Significant Bit (LSB) of the bit-pair is read-only and is always 1. You can program the Most Significant Bit (MSB) of the bit-pair to alter the triggering sensitivity as follows:

b01

Interrupt is active-HIGH level-sensitive.

b11

Interrupt is rising edge-sensitive.

See the ARM Generic Interrupt Controller Architecture Specification for more information.

Private Peripheral Interrupt Status Register

The GICD_PPISR characteristics are:

Purpose

Enables a Cortex-A7 MPCore processor to access the status of the PPI inputs on the Distributor. Non-secure accesses can only read the status of Group 1 interrupts.

Usage constraints

A processor can only read the status of its own PPI and therefore cannot read the status of the PPI for other processors. .

Configurations

Available if the GIC is implemented.

Attributes

See the register summary in Table 8.3.

Figure 8.3 shows the GICD_PPISR bit assignments.

Figure 8.3. GICD_PPISR bit assignments

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Table 8.6 shows the GICD_PPISR bit assignments.

Table 8.6. GICD_PPISR bit assignments

Bits Name Description
[31:16] - Reserved, RAZ
[15:9] PPI status

Assert when the PPI [6:0] inputs to the Distributor are asserted:

PPI6

Virtual Maintenance Interrupt.

PPI5

Hypervisor timer event.

PPI4

Virtual timer event.

PPI3

nIRQ.

PPI2

Non-secure physical timer event.

PPI1

Secure physical timer event.

PPI0

nFIQ.

Note

These bits return the actual status of the PPI[6:0] signals. The GICD_ISPR and GICD_ICPR can also provide the PPI[6:0] status, although you can write to these registers, they might not contain the true status of the PPI input signals.

[8:0]-Reserved, RAZ

Shared Peripheral Interrupt Status Registers

The GICD_SPISRn characteristics are:

Purpose

Enables a Cortex-A7 MPCore processor to access the status of IRQS[479:0] signals on the Distributor.

Usage constraints

Non-secure accesses can only read the status of Group 1 interrupts.

Configurations

Available if the GIC is implemented.

Attributes

See the register summary in Table 8.3.

Figure 8.4 shows the GICD_SPISRn register bit assignments.

Figure 8.4. GICD_SPISRn bit assignments

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Table 8.7 shows the GICD_SPISRn register bit assignments.

Table 8.7. GICD_SPISRn bit assignments

Bits Name Function
[31:0] IRQS[N+31:N]

Returns the status of the IRQS[479:0] signals on the Distributor. For each bit:

0

IRQS is LOW.

1

IRQS is HIGH.

Note

  • The IRQS that a bit refers to depends on its bit position and the base address offset of the GICD_SPISRn.

  • These bits return the actual status of the IRQS[479:0] signals. The GICD_ISPENDRn and GICD_ICPENDRn can also provide the IRQS[479:0] status, although you can write to these registers, they might not contain the actual status of the IRQS[479:0] signals.


Figure 8.5 shows the address map that the Distributor provides for the SPIs.

Figure 8.5. GICD_SPISRn address map

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The Distributor provides up to 15 registers to support 480 SPIs. If you configure the GIC to use fewer than 480 SPIs, it reduces the number of registers accordingly. For locations where interrupts are not implemented, the bit is RAZ/WI.

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