5.1. About the MMU

The Cortex-A7 MPCore processor implements the Extended VMSAv7 MMU, which includes the ARMv7-A Virtual Memory System Architecture (VMSA), the Security Extensions, the Large Physical Address Extensions (LPAE), and the Virtualization Extensions.

The Extended VMSAv7 MMU controls address translation, access permissions, and memory attributes determination and checking, for memory accesses.

See the ARM Architecture Reference Manual for a full architectural description of the Extended VMSAv7.

The MMU controls table walk hardware that accesses translation tables in main memory. The MMU works with the L1 and L2 memory system to translate virtual addresses to physical addresses. The MMU enables fine-grained memory system control through a set of virtual-to-physical address mappings and memory attributes held in the Translation Look-aside Buffers (TLBs).

The MMU features in each processor of the multiprocessor device include the following:

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