4.3.30. Normal Memory Remap Register

The NMRR characteristics are:

Purpose

Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in the PRRR.

Usage constraints

The NMRR is:

Configurations

The NMRR:

  • Is Banked.

  • Has write access to the Secure copy of the register disabled when the CP15SDISABLE signal is asserted HIGH.

Attributes

See the register summary in Table 4.11.

Figure 4.26 shows the NMRR bit assignments.

Figure 4.26. NMRR bit assignments

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Table 4.59 shows the NMRR bit assignments.

Table 4.59. NMRR bit assignments

BitsNameDescription
[2n+17:2n+16][a]ORn

Outer Cacheable property mapping for memory attributes n, if the region is mapped as Normal memory by the PRRR.TRn entry. n is the value of the TEX[0], C and B bits, see Table 4.54. The possible values of this field are:

0b00

Region is Non-cacheable.

0b01

Region is Write-Back, Write-Allocate.

0b10

Region is Write-Through, no Write-Allocate.

0b11

Region is Write-Back, no Write-Allocate.

See Table 5.2 for more information about this field.

[2n+1:2n][a]IRn

Inner Cacheable property mapping for memory attributes n, if the region is mapped as Normal Memory by the PRRR.TRn entry. n is the value of the TEX[0], C and B bits, see Table 4.54. The possible values of this field are the same as those given for the ORn field.

See Table 5.2 for more information about this field.

[a] Where n is 0-7


To access the NMRR, read or write the CP15 register with::

MRC p15, 0, <Rt>, c10, c2, 1    ; Read Normal Memory Remap Register 
MCR p15, 0, <Rt>, c10, c2, 1    ; Write Normal Memory Remap Register
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